Method of forming a bit line over capacitor array of memory cell

Details Method of forming a bit line over capacitor array of memory cell Method of forming a bit line over capacitor array of memory cell

1996-10-16

1998-10-13

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438243, 438252, H01L 718242

Patent

active

058211403

ABSTRACT:
A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the active areas; g) a bit line plug extending through the insulating layer and electrically interconnecting the bit line with the other active area, the bit line plug comprising an electrically conductive annular ring. Integrated circuitry, beyond memory devices, utilizing an annular interconnection ring are also disclosed. Such constructions having additional radially inward insulating annular rings and conductive rings are also disclosed. A method of forming a bit line over capacitor array of memory cells having such rings is also disclosed.

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IBM Technical Disclosure Bulletin, "Method For Making Verical Coaxial Wiring", vol. 32, No. 12, May 1990, pp. 443-444.

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