Memory device communication line control

Details Memory device communication line control Memory device communication line control

1997-11-20

1999-02-23

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Precharge

365149, G11C 700

Patent

active

058751408

ABSTRACT:
A memory device is described which equilibrates and precharges the input/output lines synchronously during a write cycle and asynchronously during a read cycle. During a read cycle, the timing of equilibration and precharge functions are decoupled from the clock signal and asynchronously initiate the equilibrate and precharge functions of the I/O lines in response to a latch signal. The invention initiates the equilibration and precharging of the I/O lines earlier in the access cycle thereby increasing memory access speed.

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"Micron 4 MEG .times. 4/2 MEG .times. 8 SDRAM", Micron Synchronous DRAM Data Book, Micron Technology, Inc., 1-44, (Rev. Feb. 1997.).

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