Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-20
2003-11-18
Tran, Thien (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S317000, C257S321000
Reexamination Certificate
active
06649969
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a semiconductor device and the fabrication process for the same. More specifically, the present invention relates to a structure of a nonvolatile semiconductor device having a floating gate and the fabrication process for the same.
2. Description of the Prior Art
FIG. 11
is a cross section view of a conventional AND type nonvolatile semiconductor device
110
. The nonvolatile semiconductor device
110
is a flash memory, or the like. Here, though not shown, an element isolation region and a peripheral circuit region are formed on both sides of a cell. The nonvolatile semiconductor device
110
has a T-shape floating gate
112
and a control gate
113
embedded in an oxide film (for example, TEOS film) deposited by chemical vapor deposition (hereinafter referred to as CVD) on a substrate
111
. By adopting the T-shape floating gate
112
, the overlapped area between the floating gate
112
and the control gate
113
can be increased. As a result, the capacitance between the floating gate
112
and the control gate
113
can be larger.
The reason for increasing the capacitance between the floating gate
112
and the control gate
113
is to improve the performance of the cell by increasing the coupling between the floating gate
112
and the control gate
113
. In the following, a more detailed description is given. The capacitance between the floating gate
112
and the control gate
113
is denoted as C
1
while the capacitance between the floating gate
112
and the substrate
111
is denoted as C
2
. For example, the larger C
1
becomes in comparison with C
2
the lower is the gate voltage for carrying out the writing operation or the erasing operation. In other words, the larger C
1
becomes in comparison with C
2
the shorter the writing time and the erasing time can be made with the same gate voltage, that is to say, the performance of the cell is increased. Accordingly, it is better the capacitance C
1
between the floating gate
112
and the control gate
113
to be increased and, in addition, it is also better the capacitance C
2
between the floating gate
112
and the substrate
111
to be decreased.
Capacitance C
2
is formed mainly of two capacitances, that is, a capacitance C
2
-
a
between the axis part (part in the vertical direction) of the T-shape floating gate
112
and the substrate
111
and a capacitance C
2
-
b
between the arm part (part in the horizontal direction) of the T-shape floating gate
112
and the substrate
111
. Capacitance C
2
-
a
corresponds to a capacitance of a so-called tunnel region in a nonvolatile semiconductor, which is an essentially necessary part for the cell. On the other hand, capacitance C
2
-
b
is a so-called parasitic capacitance which is essentially irrelevant to the operation of the cell.
Accordingly, when the capacitance C
2
-
b
becomes smaller in the capacitance C
2
, the coupling between the floating gate
112
and the control gate
113
is increased so as to increase the performance of the cell.
In the structure of a conventional nonvolatile semiconductor device
110
, however, it is difficult to make the parasitic capacitance C
2
-
b
small. As for a more detailed description, it is desirable to make the distance between the arm part of the floating gate
112
and the substrate
111
larger, that is to say, to make the position of the arm part of the floating gate
112
higher above the substrate
111
in order to make the parasitic capacitance C
2
-
b
small. However, it is difficult to make the position of the arm part higher because of the restriction of the gate etching process.
As for the description of the reason why the position of the arm part cannot be made higher, first, in the case that the position of the arm part is made higher, the length of the axis part, which is to be etched, inevitably increases in the vertical direction. In the etching process, generally, process dispersion, or the like, is taken into consideration and an over-etching of the actual amount of the object to be etched is carried out according to a predetermined ratio. Accordingly, in the case that the position of the arm part is made higher the etching amount increases because the etching distance becomes longer and over-etching is carried out. The gate etching, however, must be completed in the etching time to the degree where the tunnel oxide film, which exists under the gate, does not undergo penetration. In the case that the etching time is set for a long period of time, the tunnel oxide film is penetrated at the time of etching so as to cause an operation defect of the cell. And, in the case that the etching time is set for a short period of time, the gate material which must be etched remains so as to cause a short circuit between the cells. Accordingly, the etching time has an upper limit and a lower limit. Therefore, the etching distance of the axis part cannot be increased (position of the arm part cannot be made higher) without causing a decrease in the yield due to process dispersion.
In addition, the relative dielectric constant of the CDV oxide film
114
, which exists between the floating gate
112
and the substrate
111
, is approximately 4 so as to be a factor for increasing the parasitic capacitance.
SUMMARY OF THE INVENTION
An object of the present invention is to reduce parasitic capacitance between the floating gate and the substrate in a non-volatile semiconductor device without lowering the yield.
According to the first aspect of the invention, a process for fabricating a nonvolatile semiconductor device comprising a control gate and a floating gate having a fin part and an axis part is provided. The fabrication process comprises the steps of providing a substrate; forming a first insulating layer on the substrate; forming an axis part, made of a conductive material, of a floating gate on the first insulating layer; forming a source electrode and a drain electrode in the substrate; depositing an absorbent material on the first insulating layer and in the proximity of said formed axis part; forming a fin part, made of said conductive material, of the floating gate on said absorbent material to connect to said axis part ; forming a second insulating layer on said fin part; forming a control gate, made of a conductive material, on the formed second insulating layer; and etching said deposited absorbent material in a gas atmosphere to form a void area beneath the fin part.
According to the second aspect of the invention, a process for fabricating a nonvolatile semiconductor device comprising a control gate and a floating gate having a fin part and an axis part is provided. The fabrication process comprises the steps of providing a substrate; forming a first insulating layer on the substrate; forming an axis part, made of a conductive material, of a floating gate on the first insulating layer; forming a source electrode and a drain electrode in the substrate; depositing a material having relative dielectric constant of 3 or less, on the first insulating layer and in the proximity of said layered axis part; forming a fin part, made of said conductive material, of the floating gate on said material having relative dielectric constant of 3 or less to connect to said axis part; forming a second insulating layer on said fin part; and forming a control gate, made of a conductive material, on the formed second insulating layer. As a result, a layer of a material having a relatively low relative dielectric constant is formed beneath the fin of the floating gate.
It is an advantage of the invention that the absolute value of the parasitic capacitance between the floating gate and the substrate is decreased and that a nonvolatile semiconductor device of high performance can be obtained without lowering the yield.
It is another advantage of the invention that the degree of the fluctuation of the parasitic capacitance due to the manufacturing process can be restricted to a low level and a nonvolatile semiconductor device of
Teramoto Akinobu
Tsuji Naoki
Wakao Kazutoshi
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Tran Thien
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