Method of fabricating a non-volatile memory with a spacer

Details Method of fabricating a non-volatile memory with a spacer Method of fabricating a non-volatile memory with a spacer

2001-12-04

2003-02-25

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S287000, C438S595000

Reexamination Certificate

active

06524913

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method of fabricating a non-volatile memory.
2. Description of Related Art
A non-volatile memory is capable of retaining stored data even if the power is turned off and has the advantages of being light in weight and minute in dimension, therefore its use is becoming more and more widespread. The early non-volatile memory used the polysilicon floating gate as the storage unit, in which only one bit can be stored since polysilicon is a conductive material and the charges stored will delocalize into the whole floating gate. Recently, non-volatile memory having a nitride layer as a charge storage layer, such as NROM (nitride ROM) or SONOS (Substrate-Qxide-Nitride-Qxide-Silicon) memory, has been proposed. Since the insulating nitride layer is used as the charge storage layer in such a memory, the charges trapped in the charge storage layer will not delocalize, thereby each memory cell can have two bits stored.
Refer to
FIG. 1
, which illustrates the structure of the conventional SONOS memory cell and the positions of the data storage regions in the SONOS memory cell. As shown in
FIG. 1
, the conventional SONOS memory cell includes a substrate
100
, a silicon oxide layer
110
, a silicon nitride layer
120
, a silicon oxide layer
130
, a polysilicon gate
140
, and two doped regions
150
&
160
that are located in the substrate
100
beside the polysilicon gate
140
and serve as a source region and a drain region. The silicon oxide layer
110
, the silicon nitride layer
120
, and the silicon oxide layer
130
together are called a charge-trapping layer
138
. Two data storage regions
170
and
180
are located at two ends of the silicon nitride layer
120
under the polysilicon gate
140
in this memory cell.
If one intends to write one bit into the data storage region
170
, it is needed to let the charges flow from the doped region
160
to the doped region
150
. Thus, the charges will flow toward the polysilicon gate
140
in the vicinity of the doped region
150
, where the electric field is strongest, and will be trapped in the data storage region
170
. On the other hand, when one wants to write one bit into the data storage region
180
, the direction of the charge current is reversed. Since the insulating nitride layer is used as the charge-trapping layer in such a memory, the charges trapped in the charge-trapping layer will not delocalize, thereby each memory cell can have two bits stored and each bit can be erased individually.
Although the data storage regions
170
and
180
can be programmed or erased respectively in the conventional SONOS memory cell, the charges previously stored in one of the data storage regions
170
(
180
) will interfere with the operation of the other. Moreover, when the dimension of the memory cell or gate linewidth is reduced, the distance between the two data storage regions
170
and
180
will decrease and the interference between them becomes even more severe. In other words, it is difficult to scale down the conventional SONOS memory cell because of the interference.
SUMMARY OF THE INVENTION
Accordingly, a method of fabricating a non-volatile memory is provided in this invention, by which the distance between the two data storage regions can be increased to decrease the interference between them under the same dimension of the memory cell.
Another object of this invention is to increase the distance between the two data storage regions in the charge-trapping layer of the non-volatile memory, so as to facilitate the miniaturization of the memory cell or the gate linewidth.
In the method of fabricating a non-volatile memory of this invention, an insulating charge-trapping layer and a plurality of bar-like conductive layers are formed on the substrate, wherein the bar-like conductive layers are to be patterned into many gates. After that, buried bit-lines are formed in the substrate between the bar-like conductive layers. Each of the buried bit-lines extends into the substrate under a portion of an adjacent high-K spacer, but not to the substrate under an adjacent bar-like conductive layer. An annealing is optionally performed. Spacers of a high-K material (high dielectric material) are then formed on the side-walls of the bar-like conductive layers. The bar-like conductive layers are afterward patterned into many gates. Subsequently, word-lines are formed over the substrate to electrically connect with the gates. The material of the high-K spacer has a dielectric constant and the high-K spacer has a width, such that a channel will extend to the substrate under the high-K spacer and connect with the buried bit-line when the non-volatile memory is operated.
Since there is a high-K spacer formed on the side-wall of the gate in this invention, the channel can extend to the substrate under the high-K spacer and connect with the adjacent buried bit-line when a voltage is applied to the gate. Thus, the charges moving in the channel can be injected into the charge-trapping layer near the buried bit-line, where the electric field is strongest. That is, the charges are stored in the data storage region within the charge-trapping layer under the high-K spacer. Thus, the distance between the two data storage regions in the charge-trapping layer increases, and the interference between them decreases. Moreover, since the distance between the two data storage regions can be increased by the method of this invention, a smaller memory cell is also feasible, i.e., it is easier to scale down the size of the memory cell (gate linewidth).
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6458661 (2002-10-01), Sung
patent: 6465303 (2002-10-01), Ramsbey et al.
patent: 2002/0086548 (2002-07-01), Chang

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