Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-09-27
2003-10-28
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S311000, C257S762000
Reexamination Certificate
active
06639263
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device, particularly to a semiconductor device having a storage capacitor and wiring including the copper element, which improves reliability and reduces manufacturing processes.
BACKGROUND OF THE INVENTION
According to recent developments of information and communication apparatus, a semiconductor device such as a DRAM (Dynamic Random Access Memory) has required higher integration and higher accumulation for semiconductor elements (hereafter referred as an element) therein. Then, as an element has been further fined, various problems have also occurred. One of the problems on a DRAM is reduction of a storage capacitance. Because the capacitance of an element is proportional to its area, if the shape of an element was made smaller simply, the capacitance decreases in proportion to the square of a machining dimension. In case that a storage capacitance of a DRAM decreases, power consumption increases and reliability deteriorates since the refreshing is frequently required for compensating disappearance of electric charges. Therefore, even if an element is fined, it is necessary to keep a storage capacitance at a certain or higher level. Up to a 16-Mbit DRAM, the reduction of the capacitance owing to the fining of an element is compensated by making an oxide film forming a capacitor thin, and then the oxide film thickness is approximately 10 nm at present. However, because the thickness of the capacitor insulation film almost reaches the limit, materials having higher dielectric constant has been developed as a capacitor insulation film for a high integration memory of 64-Mbit or more. Then, tantalum oxide (Ta
2
O
5
) is studied for 64 to 256-Mbit, and barium strontium titanate ((Ba, Sr)TiO
3
: BST) and Pb zirconate titanate (Pb(Zr, Ti)O
3
:PZT) are studied for a 1-Gbit DRAM.
Furthermore, it is necessary to pay attention to selection of an electrode material in the development of the materials configuring the capacitor insulation film. The reason is that when forming a BST or PZT film on a conventionally-used Si electrode, the electrode film is oxidized, and a dielectric film other than the BST or PZT film is formed since a BST and PZT film require high temperature and oxidation atmosphere for forming them. The insulation film formed by oxidation of an electrode film causes a problem that a designed capacitance cannot be secured. Therefore, noble metals such as platinum (Pt), ruthenium (Ru), iridium (Ir), and palladium (Pd), or ruthenium oxide superior in oxidation resistance and heat resistance are studied as materials capable of withstanding various atmospheres for forming a BST and PZT film. Moreover, since PZT is used as a capacitor insulation film not only for a DRAM but also for a FRAM (Ferroelectric Random Access Memory), Pt, Ru, Ir, Pd, RuO
2
, and IrO
2
are studied as electrode materials.
A throughput required for a semiconductor device has been severer year by year and thus, a signal delay is a problem for a device using wiring in which aluminum (Al) is used for a main conductive film. As an alternative wiring conductor to the Al wiring conductor, a wiring conductor which includes copper (Cu) having a lower electric resistance than that of Al as a main conductive film is studied. However, Cu may diffuse in a silicon oxide and thus, may deteriorate performances of a transistor.
Therefore, a barrier metal is necessary to prevent Cu from diffusing, and refractory metals such as TiN, tungsten (W), and tantalum (Ta) are studied as the barrier metal, as described in, for example, NIKKEI MICRODEVICE (pages 74 to 77 on the June issue in 1992).
Wiring using copper (Cu) for a main conductive film (hereafter referred as Cu wiring) as described in the above denotes a wiring film including the copper (Cu) element of which content is higher than contents of the other included elements.
SUMMARY OF THE INVENTION
As described above, various materials are studied on each factor configuring elements of a DRAM with improvement of integration and functions thereof. In case of developing a DRAM device, it is important to select out the material which is superior in electrical and mechanical reliabilities and can be manufactured at a low cost compared with the proposed materials. Then, the optimum materials are generally determined for respective factors.
However, if optimum materials are selected for respective factors, different materials are connected with each other at an electrical joint point between them, and thereby a problem occurs that electrical resistance increases. In case of a semiconductor device having a storage capacitor and Cu wiring, if trying to connect a plug including Cu to an extended portion of an upper electrode of the storage capacitor, the problem occurs that contact resistance increases since, for example, Ru serving as the upper electrode of the storage capacitor contacts with, for example, TiN serving as a barrier metal of the Cu wiring at the joint point and thus the different materials contact with each other.
Moreover, resistance against electromigration is deteriorated at the interface between different materials. A design rule of a DRAM has determined a dimension of 0.35 micron for a 64-Mbit DRAM. However, in case that an operation speed and integration of a device are further improved in future, it is estimated that the design rule determines a dimension of 0.25 micron for a 256-Mbit DRAM, and 0.16 micron as further fined for a 1-Gbit DRAM. Naturally, the fining at the above joint point will be further advanced and thus, it is worried that the occurrence of a void due to electromigration or disconnection becomes obvious.
Furthermore, with an aspect ratio of a plug increases, the problem occurs that a barrier metal film is not completely formed on the bottom of a contact hole. The aspect ratio of the plug is further increased as a result of making a storage capacitor structure a three-dimensionally configuration for maintaining a capacitance. As a result, it is difficult to form a barrier-metal film up to the bottom of the contact hole.
Moreover, in recent years, developments of not only a single DRAM but also a semiconductor device configured by incorporating a memory into a logic circuit, which is referred as a DRAM-consolidated logic, is advanced, and process consistency between a logic manufacturing process for mainly manufacturing a transistor and a wiring conductor connecting the transistor, and a DRAM manufacturing process for manufacturing a storage capacitor in addition to the transistor and the wiring conductor. Conventionally, a electrode film forming process of a storage capacitor, and a barrier metal film forming process for Cu wiring are different from each other since different materials are used in those processes, and as a result, it leads to high manufacturing costs.
As described above, introduction of new materials is studied for a storage capacitance and wiring of a semiconductor device such as a DRAM together with the improvement of integration and functions of an element. However, it is worried to increase contact resistance of a joint point between new different materials, to reduce electromigration resistance, to increase a manufacturing cost, and to deteriorate reliability due to introduction of a new manufacturing system or modification of a manufacturing process. Moreover, in case of a DRAM-consolidated logic having a memory circuit and a logic circuit, the consistency between a DRAM manufacturing process and a logic manufacturing process is required.
It is a first object of the present invention to provide a semiconductor device having high reliability. It is a second object of the present invention to provide a semiconductor device lowered in manufacturing costs. It is a third object of the present invention to provide a semiconductor device realizing low contact resistance at a joint point between a material of a storage capacitor electrode and a material of a Cu wiring barrier metal by adopting optimum electrode material and optimum barrier metal material. It i
Asano Isamu
Iwasaki Tomio
Kumagai Yukihiro
Miura Hideo
Ohta Hiroyuki
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Ngo Ngan V.
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