Method for plasma treating and plasma nitriding gate oxides

Details Method for plasma treating and plasma nitriding gate oxides Method for plasma treating and plasma nitriding gate oxides

2002-10-09

2003-11-18

Chen, Jack (Department: 2813)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

By reaction with substrate

C438S197000, C438S287000, C438S591000, C438S788000, C438S792000

Reexamination Certificate

active

06649538

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to CMOS device fabrication processes and, more particularly, to a method of manufacturing gate structures particularly a method for forming nitrided gate oxides having improved electrical properties including leakage current and improved charge mobility.
BACKGROUND OF THE INVENTION
Fabrication of a metal-oxide-semiconductor (MOS) integrated circuit involves numerous processing steps. A gate dielectric, typically formed from silicon dioxide, is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate electrode is formed over the gate dielectric, and dopant impurities are introduced into the semiconductor substrate to form source and drain regions. Many modern day semiconductor microelectronic fabrication processes form features having less than 0.25 critical dimensions, for example more recent devices include features sizes of less than 0.13 microns. As feature size decreases, the size of the resulting transistor as well as transistor features also decrease. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single die area.
In semiconductor microelectronic device fabrication, polysilicon and silicon dioxide (SiO
2
) are commonly used to respectively form gate electrodes and gate dielectrics for metal-oxide-semiconductor (MOS) transistors. As device dimensions have continued to scale down, the thickness of the SiO
2
gate dielectric layer has also decreased to maintain the same capacitance between the gate and channel regions. A thickness of the gate oxide layer of less than 2 nanometers (nm) will be required to meet smaller device design constraints. A problem with using SiO
2
as the gate dielectric is that thin SiO
2
oxide films may break down when subjected to electric fields expected in some operating environments, particularly for gate oxides less than about 50 Angstroms thick. In addition, electrons more readily pass through an insulating gate dielectric as it gets thinner due to what is frequently referred to as the quantum mechanical tunneling effect. In this manner, a tunneling current, produces a leakage current passing through the gate dielectric between the semiconductor substrate and the gate electrode, increasingly adversely affecting the operability of the device. For example, as current leakages increase the gate oxide is no longer completely capacitive and has a resistive component. As a result, the device will require a large amount of standby power, diminishing the commercial value of a device. Related to the current leakage problem in thin gate oxides, is the formation of trapping states and interfacial charged states at the silicon/gate dielectric interface which increasingly adversely affects device electrical characteristics. For example, as the trapped charges accumulate over time, the threshold voltage V
T
may shift from its design specification.
Because of high direct tunneling currents, SiO
2
films thinner than about 1.5 nm cannot be reliably used as the gate dielectric in CMOS devices. One method to counteract the effects of leakage current has been to incorporate nitrogen into the gate oxide, to increase the effective dielectric constant of the gate oxide therefore allowing a relatively thicker nitrogen doped gate oxide to be formed with a capacitance comparable to a relatively thinner SiO
2
gate oxide. One approach in the prior art has included plasma nitriding (nitridation) methods whereby nitrogen ions are implanted into the surface of the gate oxide after forming a thin thermally grown SiO
2
layer, for example about 50 Angstroms to about 150 Angstroms. Other methods of nitriding of the gate oxide have additionally been proposed including thermally growing gate oxides in the presence of ammonia (NH
3
) or in the presence of nitrous oxide (N
2
O) in a rapid thermal oxidation (RTO) process. Through the provision of an NH
3
ambient during oxide growth, nitrogen can be incorporated at concentration levels up to about 10 wt % while growing oxides in an N
2
O ambient results in a lower wt % nitrogen incorporated into the gate oxide, for example about 1 to about 2 wt %. A shortcoming of using NH
3
as a ambient for nitriding is the presence of hydrogen in the gate oxide creating electron trapping sites which can increase current leakage. A shortcoming of the using N
2
O as an ambient for nitriding is the limited amount of nitrogen that can be incorporated into the gate oxide.
Another advantage of nitriding of gate oxides, for example at the gate oxide/gate electrode interface, is the formation of a diffusion barrier for doped impurities. For example, boron is frequently used for doping polysilicon gate electrodes and tends to diffuse from across the gate oxide into the silicon substrate channel region thereby degrading device performance. An advantage of plasma nitriding has been thought to be the ability to incorporate nitrogen at the gate oxide/gate electrode interface to accomplish both the goals of creating a diffusion barrier and to reduce current leakage by increasing the dielectric constant of the gate oxide thereby allowing the formation of thicker gate oxides dielectrically equivalent to a thinner SiO
2
gate oxide, also referred to as a reduced effective oxide thickness (EOT), without the corresponding increase in tunneling (leakage) current. On the other hand, a shortcoming of this approach is the relative lack of nitrogen at the silicon/gate oxide interface which is believed to have the beneficial effect of reducing the level of trapping and interface states which contribute to current leakage. Another shortcoming of the plasma nitriding approach has been the effect of decreased charge mobility in the gate oxide resulting from nonuniform distributions of nitrogen within the gate oxide.
Therefore it would be advantageous to develop an improved method for formation of nitrided gate oxides that both reduces gate oxide current leakage while maintaining charge mobilities for improved device performance.
It is therefore an object of the invention to provide an improved method for formation of nitrided gate oxides that both reduces gate oxide current leakage while maintaining charge mobilities for improved device performance while overcoming other shortcomings and deficiencies of the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for forming a nitrided gate oxide over a silicon substrate in a semiconductor device fabrication process.
In a first embodiment, the method includes providing a silicon semiconductor substrate; thermally growing a gate oxide layer including silicon dioxide over the silicon substrate; plasma treating the gate oxide layer including a plasma supplied with a plasma source gas including at least one of helium, hydrogen, deuterium, and oxygen; plasma nitriding the gate oxide layer according to a plasma treatment including a plasma supplied with a plasma source gas including nitrogen; and, thermally annealing the silicon semiconductor substrate including the gate oxide layer according to at least one annealing treatment.


REFERENCES:
patent: 6136654 (2000-10-01), Kraft et al.
patent: 6245616 (2001-06-01), Buchanan et al.
patent: 2002/0197880 (2002-12-01), Niimi et al.

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