Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-16
2003-06-03
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06573135
ABSTRACT:
BACKGROUND
The disclosure relates to a method for manufacturing a semiconductor device and, more particularly, to a method for forming an analog capacitor and a cell capacitor simultaneously without an additional process.
BRIEF DESCRIPTION OF THE PRIOR ART
An excellent way to increase competitiveness in the semiconductor manufacturing industry is decreasing chip size by inducing a technology for fabricating fine structure in order to increase chip number per wafer, and at the same time increasing a production yield. In a dynamic random access memory (DRAM), these benefits may be obtained, but capacitance required by the DRAM unit cell is fixed, so to obtain adequate capacitance, the surface area of a cell capacitor may be secured.
As the size of the semiconductor device is minimized, two methods are introduced to secure cell capacitance. First, the height of the cell capacitor is extended to increase the surface area thereof. Second, a dielectric layer of the cell capacitor is formed of selected materials having high dielectric constant. A Ta
2
O
5
layer and/or a BST((Ba,Sr)TiO
3
) layer replace(s) a nitride layer, which is usually used as a dielectric layer.
Requirements, of the system on chip (SOC) structure have been strongly raised due to its various advantages. In particular, a technology realizing a memory device, such as DRAM, and a logic device within one chip is required, so merged DRAM with logic (MDL) and embedded DRAM with logic (EDL), etc. have been developed. Most logic circuits comprise an analog circuit and, especially, general usage of an analog capacitor has gradually been realized.
There have been numerous attempts to obtain capacitance required in the MDL. For example, the height of the capacitor may be extended, and hemispherical grains (HSG) may be formed on a surface of the charge storage electrode to increase the surface area of the capacitor. Also, electrodes of a capacitor may be formed with proper materials in order that the dielectric layer of the capacitor is formed with materials having high dielectric constants. In the case of Ta
2
O
5
, a metal insulator silicon (MIS) structure may be adopted, and in the case of other dielectric materials, such as BST, a metal insulator metal (MIM) structure may be adopted to form a capacitor.
In the tendency of manufacturing process to increase cell capacitance in the MDL, a cell capacitor having the MIM structure may be formed in a memory cell region, and an analog capacitor, of which electrodes and a dielectric layer are different from the cell capacitor, may be formed in a logic circuit region.
However, in such a process, the process complexity is increased because the cell capacitor and the analog capacitor are separately realized. Also, as the height of the cell capacitor is increased, the depth of the contact hole is consequently increased, and it is difficult to completely fill the contact hole.
Therefore, difficulties of manufacturing may be increased and lowering of reliability may occur. Moreover, Pt and Ru, which are representative materials for a capacitor electrode of a next generation DRAM, are expensive, so the materials may be effectively used, but in a conventional case, a cell capacitor and a logic capacitor are separately formed so that it is difficult to expect the effective usage of the materials.
FIGS. 1A
to
1
H are cross-sectional views illustrating a conventional semiconductor manufacturing process.
Referring to
FIG. 1A
, a well (not shown) and an isolation layer
13
of each of a cell region A and a logic region B are formed on a substrate
11
, and a gate electrode
14
and a gate hard mask
15
are then formed on the substrate
11
. The gate electrode
14
is formed from a polysilicon, a tungsten silicide, tungsten, or a combination thereof, and the gate hard mask
15
is formed of an oxide layer, a nitride layer, or a combination thereof. At this time, a logic gate is simultaneously formed in the logic region B. The logic gate has a polycide/capping layer structure and in some cases, the capping layer may be omitted.
Subsequently, a source/drain is formed using an ion injection method, etc., and a sidewall spacer
17
is formed on the gate electrode
14
and the gate hard mask
15
. Concentrations of the source/drain of the cell region A and the logic region B may be different from one another. Also, a salicide process is carried out to decrease a resistance of the source/drain
16
and a contact to be formed. The sidewall spacer
17
is formed of an oxygen layer, a nitride layer, or a combination thereof.
An interlayer insulating layer
18
is formed on the resulting structure including the gate hard mask
15
, and the interlayer insulating layer
18
is planarized.
Referring to
FIG. 1B
, a plurality of first plugs
19
of a cell region A, for example, a contact plug for storage node is formed using a polysilicon or a tungsten material, and an interlayer insulating layer
20
is deposited. Next, a bit line contact hole
21
is formed in a cell region A by selectively etching the interlayer insulating layer
20
, and in a logic region B, a contact hole
22
, which exposes the gate electrode
14
of the MOS transistor or the source/drain connection
16
, and a metal wiring contact hole are formed.
Referring to
FIG. 1C
, plugs are subsequently formed, each of which is filled into the contact holes
21
and
22
, respectively, for example, a bit line contact plug
23
and a MOS contact plug
24
, and a bit line
25
is formed in a cell region A using a tungsten or a tungsten silicide material. Subsequently, metal wiring
26
is formed in the logic region B.
Interlayer insulating layers
27
and
28
are formed on an upper portion of the resulting structure of the bit line
25
and the metal wiring
26
. In
FIG. 1C
, the interlayer insulating layer
27
for preventing oxidation and increasing adhesion of the bit line
25
, may be omitted.
Referring to
FIG. 1D
, the interlayer insulating layers
27
and
28
of the cell region A are selectively etched to formed a contact hole, which exposes a surface of the first plug
19
, and a second plug
29
is formed using a conductive material. The double plug forming technology is followed by a process to increase cell capacitance by increasing the height of a cell capacitor according to size minimization of the pattern.
Referring to
FIG. 1E
, an etching stopping layer
30
and an interlayer insulating layer
31
are successively deposited on the resulting structure including the second plug
29
and an interlayer insulating layer, and an opening portion within which a bottom electrode may be formed is formed by selectively etching an interlayer insulating layer of the cell region A and an etching stopping layer
30
. The etching stopping layer
30
is used as a masking layer in a wet etching process, so according to the selected wet etchant, the used materials are changed; a nitride layer type of material is usually used.
A conductive layer is deposited on a bottom and side portions of the opening portion, and on the interlayer insulating layer
31
using materials for a bottom electrode, such as a polysilicon and tungsten materials. Subsequently, an interlayer insulating layer
33
for covering a conductive layer of bottom and side parts of the opening portion is formed, i.e., by forming the insulating layer on the resulting structure and removing it using an etch back to leave the insulting layer within the opening portion, and carrying out a chemical mechanical polishing (CMP) process with respect to a surface of the interlayer insulating layer
28
to form a bottom electrode
32
. The insulating layer
33
prevents etching of a conductive layer forming the bottom electrode
32
, and is formed with the SOG or an oxide layer, which is used in forming a field oxide layer.
Referring to
FIG. 1F
, the bottom electrode
32
is exposed by selectively removing the interlayer insulating layer
31
on the cell region A and an insulating layer, then forming a dielectric layer
34
and a top electrode
35
. The dielectric layer
34
is usually
Elms Richard
Hynix / Semiconductor Inc.
Marshall Gerstein & Borun
Owens Beth E.
LandOfFree
Simultaneous formation of bottom electrodes and their... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Simultaneous formation of bottom electrodes and their..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Simultaneous formation of bottom electrodes and their... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3119428