Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-03
2003-02-04
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S222000
Reexamination Certificate
active
06514809
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to semiconductor-on-insulator (SOI) structures, and more specifically to partially-isolated SOI structures.
2. Description of the Related Art
Conventional or bulk semiconductor devices are formed in semiconductor material by implanting a well of either P-type or N-type conductivity silicon in a silicon substrate wafer of the opposite conductivity. Gates and source/drain diffusions are then manufactured using commonly known processes. These form devices known as metal-oxide-semiconductor (MOS) field effect transistors (FETs). When a given chip uses both P-type and N-type, it is known as a complimentary metal oxide semiconductor (CMOS). Each of these transistors must be electrically isolated from the others in order to avoid shorting the circuits. A relatively large amount of surface area is needed for the electrical isolation of the various transistors. This is undesirable for the current industry goals for size reduction. Additionally, junction capacitance between the source/drain and the bulk substrate and “off” state leakage from the drain to the source both increase power consumption. Junction capacitance also slows the speed at which a device using such transistors can operate. These problems result in difficulties in reducing the size, power consumption, and voltage of CMOS technology devices.
In order to deal with the junction capacitance and “off state” leakage problem as well as obtain reduced size, semiconductor-on-insulator technology (SOI) has been gaining popularity. A SOI wafer may be formed from a bulk silicon wafer by using conventional oxygen implantation techniques to create a buried oxide layer at a predetermined depth below the surface. The implanted oxygen oxidizes the silicon into insulating silicon dioxide in a gaussian distribution pattern centered at the predetermined depth to form the buried oxide layer. Field effect transistors formed on SOI substrates also may be able to achieve higher speed operation with higher drive currents, when compared with FETs formed on conventional bulk silicon substrates.
However, one problem with forming field effect transistors on an SOI wafer is the floating body effect. The floating body effect occurs because the buried oxide layer isolates the channel, or body, of the transistor from the fixed potential silicon substrate and therefore the body takes on charge based on recent operation of the transistor. The floating body effect causes the current-to-voltage curve for the transistor to distort or kink, which in turn causes the threshold voltage for operating the transistor to fluctuate. This problem is particularly apparent for passgate devices such as those used in dynamic random access memory (DRAM) wherein it is critical that the threshold voltage remain fixed such that the transistor remains in the “off” position to prevent charge leakage from the storage capacitor.
Another problem associated with SOI technology is heat build up. The insulating silicon dioxide in the buried oxide layer is a poor heat conductor and prevents effective heat dissipation into bulk silicon below the buried oxide layer.
Accordingly, there is a strong need in the art for a semiconductor circuit structure, and a method for forming such structure, that includes the low junction capacitance and low “off” state leakage characteristics of the SOI FET based circuits but does not-suffer the disadvantages of a floating body potential and heat build up.
SUMMARY OF THE INVENTION
A field effect transistor on an SOI wafer has a non-floating body which is tied to the substrate of the wafer by a bridge of conductive material such as semiconductor material. The bridge is created by selectively etching through a portion of a surface semiconductor layer and the underlying portion of a buried insulator layer, thereby making an opening or trench which exposing some of the semiconductor substrate of the SOI wafer. Then the opening is filled, for example by growth of a replacement semiconductor material by selective epitaxy.
According to an aspect of the invention, a method of forming a semiconductor device includes the steps of exposing a portion of a semiconductor substrate of a semiconductor-on-insulator wafer by removing overlying portions of a surface semiconductor layer and of a buried insulator layer between the substrate and the surface semiconductor layer, thereby forming an opening perforating the surface semiconductor layer and the buried insulator layer; and filling the opening with conductive material to thereby electrically connect the substrate and the surface layer.
According to another aspect of the invention, a method of forming a semiconductor device includes the steps of forming a dummy gate on an active region of a surface semiconductor layer which is separated from a semiconductor substrate by an intervening buried insulator layer; selectively doping portions of the active region to form a source and a drain on opposite sides of a body, using the dummy gate as a doping mask; removing the dummy gate; exposing a portion of a semiconductor substrate of a semiconductor-on-insulator wafer by removing overlying portions of the active layer and of the buried insulator layer, thereby forming an opening perforating the surface semiconductor layer and the buried insulator layer, wherein the exposing includes etching the active region and the insulating layer through a space left by removal of the dummy gate; and epitaxially growing a semiconductor material to fill the opening and thereby electrically connect the substrate and the body.
According to yet another aspect of the invention, a semiconductor device includes an active semiconductor region including a source and a drain with a body therebetween; a gate atop the active region and operatively coupled to the source, the body and the drain; a buried insulator layer between the active region and an underlying semiconductor substrate, wherein the buried insulator layer has a perforation therein a semiconductor bridge in the perforation, the bridge in contact with the body and the substrate, and electrically connecting the body and the substrate wherein the bridge and at least part of the body include epitaxially-grown semiconductor material.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
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Meier Stephen D.
Renner , Otto, Boisselle & Sklar, LLP
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