Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2002-10-09
2003-11-11
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S738000, C714S744000
Reexamination Certificate
active
06647523
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to integrated circuit devices, and more particularly to a method and circuit utilizing a first captured bit stream in generating expect data for subsequent captured bit streams.
BACKGROUND OF THE INVENTION
A conventional computer system includes a processor coupled to a variety of memory devices, including read-only memories (“ROMs”) which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The system memory generally includes dynamic random access memory (“DRAM”), and in many modern computer systems includes synchronous DRAMs (“SDRAMs”) to enable the processor to access data at increasingly faster rates. One skilled in the art will appreciate, however, that a large speed disparity subsists between the operating speed of modern processors and that of modern SDRAMs. This speed disparity limits the rate at which the processor can access data stored in the SDRAMs, which is a common operation, and consequently limits the overall performance of the computer system. For example, modem processors, such as the Pentium® and Pentium II® microprocessors, are currently available operating at clock speeds of at least 400 MHz, while many SDRAMs operate at a clock speed of 66 MHz, which is a typical clock frequency for controlling system memory devices.
A solution to this operating speed disparity has been proposed in the form of a computer architecture known as a synchronous link architecture. In the synchronous link architecture, the system memory devices operate at much higher speeds and may be coupled to the processor either directly through the processor bus or through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, synchronous link memory devices receive command packets that include both control and address information. The synchronous link memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus.
A typical synchronous link dynamic random access memory (“SLDRAM”) memory device
16
is shown in block diagram form in FIG.
1
. The memory device
16
includes a clock generator circuit
40
that receives a command clock signal CCLK and generates a large number of other clock and timing signals to control the timing of various operations in the memory device
16
. The memory device
16
also includes a command buffer
46
and an address capture circuit
48
which receive an internal clock signal ICLK, a command packet CA<
0
:
39
> in the form of 4 packet words CA<
0
:
9
> applied sequentially on a 10 bit command-address bus CA, and a terminal
52
receiving a FLAG signal. A synchronization circuit
49
is part of the command buffer
46
, and operates during a synchronization mode to synchronize the command clock signal CCLK and two data clock signals DCLK
0
and DCKL
1
, as will be explained in more detail below.
A memory controller (not shown) or other device normally transmits the command packet CA<
0
:
39
> to the memory device
16
in synchronism with the command clock signal CCLK. The command packet CA<
0
:
39
> contains control and address information for each memory transfer. The FLAG signal identifies the start of a command packet CA<
0
:
39
>, and also signals the start of an synchronization sequence. The command buffer
46
receives the command packet CA<
0
:
39
> from the command-address bus CA, and compares at least a portion of the command packet to identifying data from an ID register
56
to determine if the command packet is directed to the memory device
16
or some other memory device (not shown). If the command buffer
46
determines that the command is directed to the memory device
16
, it then provides the command to a command decoder and sequencer
60
. The command decoder and sequencer
60
generates a large number of internal control signals to control the operation of the memory device
16
during a memory transfer.
The address capture circuit
48
also receives the command packet from the command-address bus CA and outputs a 20-bit address corresponding to the address information in the command packet. The address is provided to an address sequencer
64
, which generates a corresponding 3-bit bank address on bus
66
, a 10-bit row address on bus
68
, and a 7-bit column address on bus
70
. The row and column addresses are processed by row and column address paths, as will be described in more detail below.
One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The memory device
16
largely avoids this problem by using a plurality of memory banks
80
, in this case eight memory banks
80
a-h
. After a read from one bank
80
a
, the bank
80
a
can be precharged while the remaining banks
80
b-h
are being accessed. Each of the memory banks
80
a-h
receives a row address from a respective row latch/decoder/driver
82
a-h
. All of the row latch/decoder/drivers
82
a-h
receive the same row address from a predecoder
84
which, in turn, receives a row address from either a row address register
86
or a refresh counter
88
as determined by a multiplexer
90
. However, only one of the row latch/decoder/drivers
82
a-h
is active at any one time as determined by bank control logic
94
as a function of a bank address from a bank address register
96
.
The column address on bus
70
is applied to a column latch/decoder
100
, which supplies I/O gating signals to an I/O gating circuit
102
. The I/O gating circuit
102
interfaces with columns of the memory banks
80
a-h
through sense amplifiers
104
. Data is coupled to or from the memory banks
80
a-h
through the sense amps
104
and I/O gating circuit
102
to a data path subsystem
108
which includes a read data path
110
and a write data path
112
. The read data path
110
includes a read latch
120
that stores data from the I/O gating circuit
102
. In the memory device
16
, 64 bits of data, which is designated a data packet, are stored in the read latch
120
. The read latch then provides four 16-bit data words to an output multiplexer
122
that sequentially supplies each of the 16-bit data words to a read FIFO buffer
124
. Successive 16-bit data words are clocked into the read FIFO buffer
124
by a clock signal RCLK generated from the internal clock signal ICLK. The 16-bit data words are then clocked out of the read FIFO buffer
124
by a clock signal obtained by coupling the RCLK signal through a programmable delay circuit
126
. The programmable delay circuit
126
is programmed during synchronization of the memory device
16
so that the data from the memory device is received by a memory controller, processor, or other device (not shown) at the proper time. The FIFO buffer
124
sequentially applies the 16-bit data words to a driver circuit
128
which, in turn, applies the 16-bit data words to a data bus DQ. The driver circuit
128
also applies one of two data clock signals DCLK
0
and DCLK
1
to respective data clock lines
132
and
133
. The data clocks DCLK
0
and DCLK
1
enable a device, such as a processor, reading the data on the data bus DQ to be synchronized with the data. Particular bits in the command portion of the command packet CA<
0
:
39
> determine which of the two data clocks DCLK
0
and DCLK
1
is applied by the driver circuit
128
. It should be noted that the data clocks DCLK
0
and DCLK
1
are differential clock signals, each including true and complementary signals, but for ease of explanation, only one signal for each clock is illustrated and described.
The write data path
112
includes a receiver buffer
140
coupled to the data bus
130
. The receiver buffer
140
sequentially applies 16-bit data words from the data bus DQ to four input registers
142
, each of which is selectively enabled by a signal from a clock generato
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Ton David
LandOfFree
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