Storage electrode of a semiconductor memory device and...

Details Storage electrode of a semiconductor memory device and... Storage electrode of a semiconductor memory device and...

2001-12-12

2003-06-24

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S253000, C438S396000

Reexamination Certificate

active

06583056

ABSTRACT:

CROSS REFERENCES TO RELATED APPLICATIONS
This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2001-10972, filed on Mar. 3, 2001, the entirety of which is hereby incorporated by reference herein for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a storage electrode and a method for fabricating the same, and more particularly to a high storage electrode having a stable structure which can be prevented from falling down when installed in a limited cell area, and a method for fabricating the same.
2. Description of the Related Art
Recently, as the integration degree of a memory device, such as a DRAM, increases various methods are studied and developed for obtaining sufficient capacitance in a limited cell area. In order to increase the cell capacitance, a material having a high dielectric constant is used as a capacitor dielectric layer, an effective area of a cell capacitor is enlarged by growing an HSG (hemisphere silicon grain), and/or a high dielectric material is used as a dielectric layer.
Besides the HSG method, in which the effective area is enlarged by a concave and convex surface structure, a technique for raising the height of a storage electrode layer forming the cell capacitor is introduced in order to enlarge the effective area of the cell capacitor. Since the HSG process is complicated and increases the manufacturing cost, techniques for raising the height of the storage electrode of a capacitor are being studied and developed.
In order to obtain sufficient cell capacitance in a small cell area, a capacitor having a height more than 15,000 Å is introduced into the gigabit DRAM. As the cell area becomes smaller, the height of the capacitor is relatively increased so that the storage electrode is tilted or, in an extreme case, falls down.
Generally, in a cylindrical capacitor, an opening is formed in an insulating layer and a cylindrical storage electrode is formed along the profile of a bottom and a sidewall of the opening. The bottom of the opening formed in the insulating layer is relatively narrower than an inlet of the opening due to a loading effect created during an etching process. Accordingly, the sidewall of the opening is sloped.
Polysilicon is coated on the bottom and the sidewall of the opening along the profile of the opening, so that a polysilicon storage electrode layer has an unstable structure. That is, a bottom portion of the polysilicon storage electrode layer is narrower than an inlet portion of the polysilicon storage electrode layer. In addition, when a peripheral insulating layer is removed, the sidewall of the storage electrode layer has a reverse-inclination so that the storage electrode layer is tilted due to the weight thereof and easily falls down if an impact is applied thereto when a wafer is moved for the following process.
A method for fabricating a cylindrical storage electrode will be described with reference to
FIGS. 1
to
3
.
FIGS. 1
to
3
are sectional views showing the process steps for forming a cylindrical storage electrode layer of a semiconductor memory device.
Referring to
FIG. 1
, in order to provide a DRAM cell, a trench type field oxide layer
12
is formed on a silicon substrate
10
and an active device is formed in an active area. Generally, the active device is a metal oxide semiconductor (MOS) transistor.
The MOS transistor includes a gate electrode having a stacked structure of a polysilicon layer
16
and a tungsten silicide layer
18
formed on a gate oxide layer
14
. The gate electrode is protected by a sidewall spacer
20
and a mask layer
32
which are comprised of insulating materials. Source and drain regions are formed by implanting impurities into surface portions of the active area of the silicon substrate
10
by using a gate electrode layer as an ion implanting mask.
Self-aligned contact holes are formed for the drain and source regions. Then, a conductive material, such as doped-polysilicon, is filled in the contact hole so as to form contact plugs
24
and
26
.
Then, the MOS transistor is covered with an insulating layer
28
and the surface of the insulating layer
28
is polished by means of a chemical mechanical polishing (CMP) process.
After forming a bit line contact in the insulating layer
28
and exposing a drain contact plug
24
, a bit line
30
is formed. The bit line
30
is protected by a sidewall spacer
32
and a mask layer
34
which are comprised of insulating materials.
The surface formed with the bit line
30
is coated with an insulating layer
36
. Then, the surface of the insulating layer
36
is polished by means of the CMP process.
An opening is formed in the insulating layer
36
by a photolithography process. Then, a buried contact plug
37
is formed by filling polysilicon into the opening.
An etching stop layer
38
is formed by coating a nitride layer on the insulating layer
36
. Then, an insulating layer
40
having a thickness of 15,000 Å is coated on the etching stop layer
38
and a photoresist pattern
42
for defining a capacitor forming area is formed thereon.
An opening
44
is formed by anisotropically and sequentially etching the insulating layer
40
and the anti-reflective layer
36
using the photoresist pattern as an etching mask. Accordingly, an upper surface of the buried contact plug
37
is exposed at a bottom
44
b
of the opening
44
.
At this time, the bottom
44
b
of the opening
44
is narrower than an inlet
44
a
of the opening
44
. That is, the bottom critical dimension becomes narrower than the critical dimension of the opening. Therefore, the sidewalls of the opening
44
are sloped. The reason is that the etching rate of the bottom is lower than the etching rate of the inlet due to the loading effect generated during the etching process. The loading effect extremely appears as the depth of the opening becomes deeper, that is as the height of the storage electrode layer becomes higher.
Referring to
FIG. 2
, after stripping the photoresist pattern
42
which is used as the etching mask, a polysilicon layer
46
is coated to a uniform thickness along a profile of the insulating layer
40
exposed through the openings
44
.
Referring to
FIG. 3
, the polysilicon layer
46
formed on the upper surface of the insulating layer
40
is removed by performing an etch back process so that the polysilicon layer
46
is defined by each of the openings
44
. Then, the remaining insulating layer
40
is removed so that the storage electrode layer having the bottom narrower than the inlet thereof is obtained as shown in FIG.
3
.
However, the above storage electrode layer has a geometrically unstable structure due to the unbalanced structure of the inlet, the bottom and the sidewalls thereof, which is inclined so as to have a greater inlet than the bottom. For this reason, the storage electrode layer is tilted caused by the weight thereof, or, in extreme case, the storage electrode layer falls down thereby causing the failure of the cell.
If the storage electrode layer is tilted towards an adjacent storage electrode layer, a two-bit error may occur so that the reliability of a semiconductor device is lowered.
In addition, if the storage electrode layer falls down, the cell fails so that the yield rate of the semiconductor device is lowered.
SUMMARY OF THE INVENTION
Therefore, it would be desirable to provide a storage electrode of a semiconductor memory device having a geometrically stable structure, in which a base of the storage electrode layer is larger than a top of the storage electrode layer.
It would also be desirable to provide a method which is suitable for fabricating the above storage electrode.
The present invention has been made to address the above problems of the prior art. Other objects and advantages will appear hereafter.
In one aspect of the invention, there is provided a storage electrode of a semiconductor memory device. The storage electrode has a cylindrical base section having a first inner diamet

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