Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-03-27
2003-10-21
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000, C438S266000, C438S267000
Reexamination Certificate
active
06635533
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a method of fabricating flash memory.
2. Background of the Invention
The memory device is a semiconductor device used for storing information or data. When the functions of the microprocessor increase and a large amount of programs and operations are required to be executed by the software, the demand for the memory increases. To satisfy this demand, fabricating high-capacity and inexpensive memory devices has become a driving force challenging high integration technique and process.
Flash memory, which is a non-volatile memory, can perform programming, erasing and reading many times and can retain information even when power is interrupted, so it is widely used in personal computers and electrical apparatus.
In the typical flash memory cell, the floating gate and the control gate are made of doped polysilicon. The floating gate and the control gate are isolated by a dielectric layer, and the floating gate is isolated from the substrate by a tunnel oxide layer. During the writing/erase operation, electrons are injected into/ejected from the floating gate with a voltage is applied to the control gate and the source/drain region. During the reading operation, a working voltage is applied to the control gate. At this time, the charging state on the floating gate causes a conducting status of ON or OFF of the channel under the floating gate. The conducting state of ON/Off corresponds to the data of
0
/
1
.
The data in the above mentioned flash memory is erased by increasing the potential of the substrate, the drain/source, or the control gate, relative to the floating gate. The electrons ejected from the floating gate flow into the substrate or the drain/source via the tunnel oxide layer by tunneling. This mechanism is known as the substrate erase mechanism or the drain/source side erase mechanism. Another mechanism is to eject the electrons in the floating gate to the control gate via the dielectric layer. However, the amount of the electrons ejected from the floating gate is difficult to precisely control during erasing. If too many electrons are ejected from the floating gate, the floating gate has net positive charge. This phenomenon is called “over-erasing”. When the over-erasing effect is severe, the channel under the floating gate is switched on even when the working voltage is not applied to the control gate. This may lead to an error in data reading. Therefore, to solve the over-erasing problem, a triple polysilicon gate with high-density design has been adopted in many kinds of flash memory.
As shown in
FIG. 1
, a flash memory cell is formed on a substrate
100
. The flash memory has a tunneling oxide layer
102
, a floating gate
104
, inter-gate dielectric layer
106
, control gate
108
and a capping layer
110
, wherein the floating gate
104
is under the control gate
108
. After the floating gate
104
and the control gate
108
are formed, an ion implantation process is performed to introduce impurities into the substrate
100
to form a source region
112
. A spacer
114
is formed on the sidewalls of the floating gate
104
and the control gate
108
. A polysilicon layer (non shown) is formed over the substrate
100
, and then the polysilicon layer is etched back to form a select gate
116
on the sidewall of the spacer
114
.
In the above-mentioned flash memory fabricating process, the floating gate
104
and the control gate
108
are defined by a lithographic process and an etching process. The steps are complicated and the problem of alignment control is produced. On the other hand, the device size is scaled down according to the design rule to increase the integration of the device. In order to lower the voltage applied to the control gate to improve the performance of the device, the issue of increasing the gate coupling ratio between the floating gate and control gate is very important. The gate coupling ratio can be increased by increasing the capacitance of the inter-gate dielectric layer or decreasing the capacitance of the tunneling oxide layer. The capacitance of the inter-gate dielectric layer is increased by increasing the area between the control gate and the floating gate. However, the area between the control gate and the floating gate can not be increased according to the above mentioned process and also satisfy the demand for increasing the integration of device and increasing the gate coupling ratio.
SUMMARY OF INVENTION
The present invention provides a method of fabricating flash memory, wherein a floating gate and a select gate are formed by a self alignment process to simplify the process, increase the coupling ratio between the floating gate and control gate, and improve the yield and performance of the device.
A method of fabricating a flash memory is provided. A pad layer and a mask layer are formed over the substrate, and then the mask layer is patterned for forming an opening therein. The pad layer exposed by the opening is removed. After a tunneling dielectric layer is formed on the bottom of the opening, a floating gate is formed on the sidewall of the opening. The top of the floating gate is lower than a surface of the mask layer. A source region is formed in the substrate. Thereafter, an inter-gate dielectric layer is formed in the opening and a control gate is filled in the opening. The mask layer is removed and then a gate dielectric layer is formed on the substrate and a spacer is formed on the sidewall of the floating gate and the control gate. A select gate is formed on the sidewall of the spacer. A drain region is formed in the substrate of one side of the select gate.
According to the above-mentioned, the floating gate and the select gate are formed by a self alignment means without using a photolithography process; therefore, the process window is increased and the process cost and process time are lower. Moreover, the control gate is formed by forming a conducting layer filled in the opening and then removing a part of the conducting layer besides the opening with chemical mechanical polishing or etching back until the mask layer is exposed. Since the control gate is formed without a photolithography process, the process window is increased and the process cost and process time are lower.
Moreover, since the profile from the top to one side of the floating gate is an arc, the area between the floating gate and the control gate of this invention is larger than that of the prior art. Therefore, the coupling ratio of the floating gate and the control gate is increased and the operating speed and performance of the device is improved.
In addition, since the floating gate has a sharp corner, a larger electric field is established during an erase operation to inject electrons into the select gate through the sharp corner. Therefore, erasing times are shorter and a voltage applied to the control gate is lower.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6329248 (2001-12-01), Yang
patent: 6420234 (2002-07-01), Park et al.
Chang Ko-Hsing
Hsu Cheng-Yuan
Chen Jack
Jiang Chyun IP Office
Powerchip Semiconductor Corp.
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