Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-05-29
2003-10-28
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S341000, C257S343000, C257SE29039
Reexamination Certificate
active
06639274
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of Japanese Patent Application No. 2001-162383, filed on May 30, 2001, the disclosure of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, in particular, to a low on-resistance power MOSFET or an insulated gate field effect transistor that is used in an IC exhibiting high breakdown voltage and controlling high current, for example, an IC in a switching regulator, an IC for driving an automobile electric power system, or an IC for driving a flat panel display. The present invention also relates to a method for manufacturing such a semiconductor device.
2. Description of the Related Art
The importance of power ICs containing a power MOSFET has been increasing with the rapid spread of portable apparatuses and advancements of communications technology in recent years. A power IC integrating a lateral power MOSFET with a control circuit is expected to achieve miniaturization, low power consumption, high reliability, and low cost in comparison with a conventional construction combining a discrete power MOSFET with a controlling and driving circuit. Consequently, developmental work is actively being conducted for high performance lateral power MOSFETs based on CMOS processes.
The inventor of the present invention disclosed a lateral power MOSFET having a trench structure (hereinafter referred to as a trench lateral power MOSFET) in the paper entitled “A trench lateral power MOSFET using self-aligned trench bottom contact holes” in IEDM '97 Digest, p. 359-362, 1997.
FIGS. 29 through 31
show a schematic structure of this trench lateral power MOSFET.
FIG. 29
is a plan view.
FIG. 30
is a cross sectional view along line A-A′ of FIG.
29
and shows a structure of a region for driving current as a MOSFET operation, the region being referred to as “an active region”.
FIG. 31
is a cross sectional view along line B-B′ of FIG.
29
and shows a structure of a region for leading a gate polysilicon out to a substrate surface, the region being referred to as “a gate region”.
The trench lateral power MOSFET
1
includes a p-type substrate
10
provided with a trench
11
, a gate oxide film
12
formed on a side wall region of the trench
11
, gate polysilicon
13
formed inside the gate oxide film
12
, and drain polysilicon
20
formed inside the gate polysilicon
13
through interlayer dielectric
16
and
30
. A drain region
19
that is an n-type diffusion region is formed in a bottom region of the trench
11
. A source region
17
that is an n-type diffusion region is formed in a outer peripheral region of the trench
11
. The drain region
19
is surrounded by a drain drift region
18
, which is an n-type diffusion region, surrounding the lower part of the trench
11
. The drain drift region
18
is surrounded by a p body region
21
that is a p-type diffusion region.
A p-type diffusion region
22
is formed outside the source region
17
. A p base region
23
is formed under the source region
17
. A thick oxide film
24
is formed inside the lower part of the trench
11
to secure a withstand voltage. Reference numeral
14
, in
FIGS. 29 through 31
, represents a source electrode, reference numeral
15
a drain electrode, reference numeral
25
a gate electrode, reference numerals
26
and
27
contact parts, reference numeral
28
an n-type diffusion region, and reference numeral
29
represents an interlayer oxide film.
Generally, a MOSFET is desired to have a low on-resistance per unit area. An important parameter to determine the on-resistance per unit area is a channel width per unit area. Let P to be the channel width per unit area, Wch the channel width, and A the area of the device, then P is given by Wch/A. A large P value is favorable to integrate transistors with a high density and to raise current driving ability per unit area. The P value of a conventional lateral power MOSFET without a trench structure is 0.22×10
6
[m
−1
] under the 0.6 &mgr;m rule and at breakdown voltage of 30 V class, and 0.28×10
6
[m
−1
] under the 0.35 &mgr;m rule and at breakdown voltage of 30 V class. When the trench structure as shown in
FIGS. 29 through 31
is applied, P value increases to 0.4×10
6
[m
−1
] under the 0.6 &mgr;m rule and at breakdown voltage of 30 V class, and 0.67×10
6
[m
−1
] under the 0.35 &mgr;m rule and at breakdown voltage of 30 V class by integration with higher density.
However, in the conventional trench lateral power MOSFET, over-etching during the process of making a contact hole through the interlayer dielectric at the trench bottom may cause the interlayer dielectric between the gate polysilicon and the drain polysilicon to become thinner or to disappear in the trench bottom portion of the gate region. This raises a problem of lowered breakdown voltage or short-circuit failure between the gate electrode and the drain electrode. This problem will also arise if source polysilicon is placed in the trench instead of the drain polysilicon.
In addition, the conventional trench lateral power MOSFET has trenches that are arranged in a stripe pattern. Consequently, dense integration of the channel width was not enough and possibility of lower on-resistance was left to be attained.
Parasitic capacity that affects switching characteristics of a MOSFET is chiefly formed between a gate electrode and a substrate with an intervening gate oxide film. There are three kinds of parasitic capacity: parasitic capacity between a gate and a drain Cgd, parasitic capacity between a gate and a body Cgb, and parasitic capacity between a gate and a source Cgs. To obtain favorable switching characteristics, these types of parasitic capacity should be decreased. However, because the conventional stripe pattern was formed in nearly the same proportion, the parasitic capacity was not improved. Thus, a large overlap capacity between a gate electrode and an extended drain inhibited high operating speed and low losses.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above problems, and an object of the invention is to provide a trench lateral MOSFET that exhibits excellent insulation between electrodes, low on-resistance, and high speed switching characteristics.
Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
To achieve the above object, a trench lateral MOSFET according to aspects of the present invention includes a gate region in which gate polysilicon is lead out to a substrate surface and an active region in which electric current is driven in a MOSFET operation, and a trench width in the gate region Wg is narrower than a trench width in the active region Wt, such that a source polysilicon is not formed in the trench of the gate region when a source is formed at the trench bottom of the active region and a drain polysilicon is not formed in the trench of the gate region when a drain region is formed at the trench bottom of the active region.
According to this feature of the present invention, neither source polysilicon nor drain polysilicon exists in the trench of the gate region.
A trench lateral power MOSFET according to aspects of the present invention has a planar layout of a mesh pattern. The mesh pattern includes a trench-etched region in a mesh shape and a non-trench-etched region in an island or ribbed shape left un-etched in the trench-etched region. Alternatively, the mesh pattern may include a non-trench-etched region left un-etched in a mesh shape and a trench-etched region formed in an island or ribbed shape in the non-trench-etched region. A trench width of a portion without providing a contact is thereby made smaller.
According to this feature of the invention, channel width or extended drain width per unit area of a MOSFET increases bec
Clark Jasmine
Fuji Electric & Co., Ltd.
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