Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-06-20
2003-06-03
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S626000, C438S687000, C438S693000
Reexamination Certificate
active
06573173
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor manufacturing, and more particularly to, forming a copper/tantalum interconnect over an integrated circuit (IC) using a multiple-platen CMP process.
BACKGROUND OF THE INVENTION
In the integrated circuit (IC) industry, lithographically patterned and etched aluminum interconnects are now being replaced with more advanced inlaid copper interconnects. While copper interconnects offer significant advantages over aluminum interconnects, such as improved electromigration resistance and reduced resistivity, the use of copper interconnects is exposing various unique problems in the IC industry. For example, barrier materials were not needed for aluminum interconnects. However, for copper, the industry has generally determined that barrier materials are required in order to make a high yielding copper interconnect that are reliable. Generally, tantalum barrier layers have become an optimal choice for barrier materials when creating copper interconnects. However, tantalum material requires a much different polishing slurry than copper material, whereby new cross contamination issues now exist between platens of a copper interconnect CMP system. Such contamination issues did not exist for aluminum interconnects.
In addition, it has been difficult to achieve improved planarity and reduced defectivity in many copper CMP interconnect processes. Also, due to the presence of more layers within a copper interconnect structure as compared to an aluminum interconnect structure, the throughput of copper processing needs further improvement. In addition, copper has proven to be a more environmentally sensitive material in an integrated circuit fabrication facility whereby adverse corrosion and defects due to ambient exposure and exposure to light has created certain unique manufacturing problems which now need to be addressed by the industry. These unique problems were not at issue in previous aluminum CMP processes and cannot be adequately dealt with by adopting preexisting aluminum CMP techniques.
As an example of the lack of compatibility with aluminum CMP and copper CMP, aluminum materials do not require polishing via several different chemically incompatible slurries whereby cross contamination between slurries becomes an issue. In addition, corrosive effects on aluminum when exposed to an ambient environment or to light are non-existent. Further, the aluminum buffing or polishing processes used previously in the art to perfect surface topographies in aluminum interconnects have been shown to cause significant leakage current in copper devices due to the presence of potassium. Also, the pH shock of these preexisting aluminum CMP slurries is non-optimal for use in copper processing. In fact, some prior art aluminum and copper CMP processes are adjusted to a pH range which results in significant and adverse corrosion of the copper interconnect over time. Reduction of copper corrosion is clearly desired in the industry.
Therefore, there exists in the industry a need for an improved CMP chemical mechanical polishing (CMP) process.
REFERENCES:
patent: 5340370 (1994-08-01), Cadien et al.
patent: 5389194 (1995-02-01), Rostoker et al.
patent: 5478436 (1995-12-01), Winebarger et al.
patent: 5527423 (1996-06-01), Neville et al.
patent: 5676587 (1997-10-01), Landers et al.
patent: 5739579 (1998-04-01), Chiang et al.
patent: 5770095 (1998-06-01), Sasaki et al.
patent: 5836806 (1998-11-01), Cadien et al.
patent: 5858813 (1999-01-01), Scherber et al.
patent: 5893756 (1999-04-01), Berman et al.
patent: 5897375 (1999-04-01), Watts et al.
patent: 5904159 (1999-05-01), Kato et al.
patent: 5909276 (1999-06-01), Kinney et al.
patent: 6001730 (1999-12-01), Farkas et al.
patent: 6004188 (1999-12-01), Roy
patent: 6136714 (2000-10-01), Schutz
patent: 6143656 (2000-11-01), Yang et al.
patent: 6184141 (2001-02-01), Avanzino et al.
patent: 6245663 (2001-06-01), Zhao et al.
patent: 6251789 (2001-06-01), Wilson et al.
patent: 6274478 (2001-08-01), Farkas et al.
US 6,331,134, 12/2001, Sachan et al. (withdrawn)
Chen et al., “The Investigation of Galvanic Corrosion in Post-Copper-CMP Cleaning,” IEEE 2000 International Interconnect Technology Conference, Jun. 5-7, 2000, pp. 256-258.
Anthony Brian G.
Farkas Janos
Guvenilir Abbas
Islam Mohammed Rabiul
Kolagunta Venkat
Motorola Inc.
Sarkar Asok Kumar
Vo Kim-Marie
LandOfFree
Method for forming a copper interconnect using a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a copper interconnect using a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a copper interconnect using a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3110977