Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-02-01
2003-07-22
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S301000, C257S306000, C257S532000
Reexamination Certificate
active
06597032
ABSTRACT:
RELATED APPLICATION
This application is related to Korean Application No. 99-3786, filed Feb. 4, 1999, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
This invention relates to integrated circuit devices and methods of forming integrated circuit devices and, more particularly, to integrated circuit capacitors and methods of forming integrated circuit capacitors.
BACKGROUND OF THE INVENTION
Integrated circuit devices frequently utilize on-chip capacitors as charge storage devices. Such integrated circuit devices may include memory devices having data storage capacitors therein. For example, in a dynamic random access memory (DRAM) device, each memory cell typically includes a respective storage capacitor. In these types of memory devices, the amount of charge held by each storage capacitor is a function of the value of the data written into the respective memory cell. To reliably store and read data from a memory cell, it is important that the C-V characteristics of each storage capacitor not vary significantly as a function of temperature and/or voltage applied across the capacitor.
One conventional method of forming an integrated circuit capacitor is illustrated by
FIGS. 1 and 2
a
-
2
d
. In particular,
FIG. 2
a
illustrates the steps of forming a polysilicon layer
12
on a semiconductor substrate
10
and field oxide layer (not shown). A buffer oxide layer
14
a
is also formed on the polysilicon layer
12
. The conductivity of the polysilicon layer
12
may then be increased by implanting dopants
15
through the buffer oxide layer
14
a
and into the polysilicon layer
12
. These dopants may comprise N-type dopants selected from the group consisting of arsenic (As) and phosphorus (P). A silicon nitride layer
14
b
is then deposited on the buffer oxide layer
14
a
. A layer of photoresist (not shown) is then formed on the silicon nitride layer
14
b
and patterned using conventional techniques. As illustrated by
FIG. 2
b
, a selective etching step is then performed by etching through the silicon nitride layer
14
b
, the buffer oxide layer
14
a
and the polysilicon layer
12
to expose the semiconductor substrate
10
. The resulting structure includes a polysilicon pattern
12
a
having an insulating capping layer
14
thereon.
Referring now to
FIG. 2
c
, a thermal oxidation step is performed to form thermal gate oxide layer
16
. Because silicon nitride is resistant to oxidation, the gate oxide layer
16
selectively forms on the surface of the substrate
10
and on the sidewalls of the polysilicon pattern
12
a
, but not on an upper surface of the silicon nitride layer
14
b
. A blanket layer of polycide
18
is then deposited on the substrate
10
and on the polysilicon pattern
12
a
, as illustrated.
Referring now to
FIG. 2
d
, a layer of photoresist (not shown) is the formed on the blanket layer of polycide
18
and patterned using conventional techniques. A selective etching step is then performed on the blanket layer of polycide
18
and the gate oxide layer
16
, to define a poly-insulator-poly (PIP) capacitor, having an polycide upper capacitor electrode
18
a
, and define a gate electrode
18
b
. As illustrated by
FIGS. 1 and 2
d
, the area of the upper capacitor electrode
18
a
may be smaller than the area of the lower capacitor electrode
12
a.
Unfortunately, the C-V characteristics of PIP capacitors, including those formed in accordance with the method of
FIGS. 1 and 2
a
-
2
d
, may experience significant dependence on temperature and voltage. For example, typical voltage coefficients of capacitance (VCC) and temperature coefficients of capacitance (TCC) are 200 ppm/N (part per million per volt) and 120 ppm/° C. respectively. Moreover, because PIP capacitors may comprise electrodes having relatively high resistivity, PIP capacitors may not have acceptable high frequency switching characteristics. These limitations associated with the C-V and resistance characteristics of PIP capacitors may limit the performance of integrated circuit devices (analog and digital) that utilize PIP capacitors. Thus, notwithstanding conventional techniques to form integrated circuit capacitors having polysilicon based electrodes, there continues to be a need for improved integrated circuit capacitors and methods of forming integrated circuit capacitors.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved integrated circuit capacitors and methods of forming same.
It is another object of the present invention to provide integrated circuit capacitors having excellent VCC and TCC characteristics and methods of forming same.
It is still another object of the present invention to provide integrated circuit capacitors having improved reliability and excellent high frequency characteristics and methods of forming same.
These and other objects, advantages and features of the present invention are provided by integrated circuit capacitors having a preferred metal-insulator-metal (MIM) structure and methods of forming same. The preferred methods include the use of copper damascene processing techniques. The use of these techniques improve the VCC and TCC characteristics of the capacitors relative to conventional PIP type capacitors. In particular, integrated circuit capacitors of the present invention include a first capacitor electrode comprising a first metal extending on a substrate and a first electrically insulating layer comprising a first material extending on the first capacitor electrode. The first electrically insulating layer has a first opening therein that exposes a first portion of the first capacitor electrode. An electrically insulating etch-stop layer that comprises a second material different from the first material, extends on the first electrically insulating layer and has a second opening therein. A capacitor dielectric layer extends on the exposed first portion of the first capacitor electrode and on sidewalls of the first electrically insulating layer and the etch-stop layer. A second capacitor electrode that comprises a second metal extends on the capacitor dielectric layer and opposite the first capacitor electrode. Accordingly, a MIM capacitor comprising a first capacitor electrode, capacitor dielectric layer and second capacitor electrode is formed.
According to a preferred aspect of the present invention, the capacitor dielectric layer comprises a material selected from the group consisting of plasma-enhance tetraethylorthosilicate (PE-TEOS), plasma-enhanced oxide (PEOX), plasma-enhanced silicon nitride (PESiN), silicon oxynitride (SiON), high density plasma (HDP), tantalum pentoxide (Ta
2
O
5
), spin-on glass (SOG), O
3
-TEOS and BST (BaSrTiO
3
). The first and second metals also preferably comprise copper or gold. Alternatively, the first or second metal may comprise aluminum. A preferred embodiment of the present invention may also include the use of a tungsten (W) plug that extends between the capacitor dielectric layer and the second capacitor electrode. The insulating etch-stop layer may also comprise silicon oxynitride (SiON).
Preferred methods of forming integrated circuit capacitors also comprise the steps of forming a first capacitor electrode comprising a first metal on a substrate and then forming a first interlayer insulating layer comprising a first electrically insulating material, on the first capacitor electrode. An etch-stop layer comprising a second electrically insulating material different from the first electrically insulating material, is also formed on the first interlayer insulating layer. A contact hole is then formed that extends through the etch-stop layer and the first interlayer insulating layer and exposes a portion of the first capacitor electrode. Next, a capacitor dielectric layer is formed on the exposed portion of the first capacitor electrode and on sidewalls of the first interlayer insulating layer and the etch-stop layer. The MIM capacitor structure may then be completed by forming second capacitor electrode comprising a second m
Fenty Jesse A.
Lee Eddie
Myers Bigel Sibley & Sajovec P.A.
Samsung Electronics Co,. Ltd.
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