Semiconductor device having quasi-SOI structure

Details Semiconductor device having quasi-SOI structure Semiconductor device having quasi-SOI structure

2002-07-25

2003-12-02

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S618000, C257S622000

Reexamination Certificate

active

06657258

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 99-43988, filed on Oct. 12, 1999, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to a semiconductor device having a quasi silicon-on-insulator (SOI) structure, and a manufacturing method thereof.
In general, silicon substrates are widely used in semiconductor devices. However, silicon substrates have several drawbacks. In particular, it is difficult to form a thin source/drain region and to reduce a parasitic junction capacitance that is produced in the junction area between the silicon substrate and the source/drain region. This can detrimentally effect the operation speed of the device.
Accordingly, a semiconductor device having a silicon-on-insulator (SOI) structure has been proposed. An SOI semiconductor device is constructed such that a silicon layer on which a unit device is formed is completely electrically insulated from a lower silicon substrate by an insulation layer. This reduces the capacitive coupling occurring between unit devices formed in an integrated circuit (IC) chip.
An SOI semiconductor device has a large threshold slope and exhibits little decrease in the device characteristic even at a low voltage of less than 2 V. In particular, a thin SOI device exhibits excellent characteristics, such as a decrease in the short channel effect, an increase in the sub-threshold swing, high mobility, and a decrease in the hot carrier effect, compared to existing semiconductor devices.
However, unlike in a conventional semiconductor device, in an SOI semiconductor device, an active region is isolated from a silicon substrate so that body contact is not formed, resulting in floating body effects. Floating body effects occur when excess carriers are accumulated in a floated body during device operation, and parasitic bipolar-induced breakdown or latch-up is accordingly induced.
To solve the above problems, a semiconductor device has been proposed having a quasi-SOI structure, in which a body contact is formed for extracting excess carriers by partially forming contact hole under the active region.
FIG. 1
shows a conventional semiconductor device having a quasi-SOI structure.
In detail, according to the conventional semiconductor device having a quasi-SOI structure, an oxide layer
10
is formed under a source region
3
and a drain region
5
that are to be insulated from a lower silicon substrate
1
. However, the body region under a channel region is opened so that it is not insulated from the lower silicon substrate
1
. As a result, a body contact can be formed in the same manner as in a bulk device. In
FIG. 1
, reference numerals
2
,
7
and
9
denote a field oxide layer, a gate oxide layer, and a gate electrode, respectively.
In the conventional SOI semiconductor device, the oxide layer
10
is formed by implanting oxygen ions using the gate electrode
9
as a mask and then performing high-temperature annealing on the resultant structure. However, since the gate oxide layer
7
or the ion implanted state of the channel region may be affected by ion implantation or annealing, the conventional SOI semiconductor device has drawbacks in practical fabrication.
SUMMARY OF THE INVENTION
It is, therefore, an objective of the present invention to provide a semiconductor device having a quasi-SOI structure with a body contact capable of suppressing floating body effects while solving the problems set forth above.
It is another objective of the present invention to provide a method suitable for manufacturing the semiconductor device having such a quasi-SOI structure.
Accordingly, to achieve the first objective, a semiconductor device having a silicon-on-insulator (SOI) structure, includes a lower silicon substrate; an upper silicon pattern formed over the lower silicon substrate; a reverse T-type hole formed between the upper silicon pattern and the lower silicon substrate; an isolating insulation layer formed in the reverse T-type hole for partially electrically insulating the upper silicon pattern from the lower silicon substrate; a gate insulation layer and a gate electrode formed over the upper silicon pattern; a source region formed in the upper silicon pattern adjacent to the gate electrode; a drain region formed in the upper silicon pattern adjacent to the gate electrode; a channel region formed in the upper silicon pattern between the source and drain regions; and a silicon layer formed under the channel region for electrically connecting the lower silicon substrate and the upper silicon pattern.
The silicon layer is preferably a porous silicon layer. An air layer may be formed in the isolating insulation layer below the upper silicon pattern. The upper silicon pattern is preferably a single-crystal silicon layer.
To achieve the second objective, in the present invention, a method is provided for manufacturing a semiconductor device having an SOI structure. In this method, a porous silicon pattern is formed over a lower silicon substrate. An upper silicon pattern is then formed over the a porous silicon pattern. A hole is then formed in the upper silicon pattern and the porous silicon pattern to expose the lower silicon substrate. A reverse T-type hole and an undercut porous silicon pattern are then formed under the upper silicon pattern by partially etching the porous silicon pattern, the resulting undercut porous silicon pattern partially electrically contacting the lower silicon substrate and the upper silicon pattern. The lower silicon substrate is partially electrically isolated from the upper silicon pattern by forming an isolating insulation layer in the reverse T-type hole. A gate insulation layer and a gate electrode are formed over the upper silicon pattern, and source and drain regions are formed in the upper silicon pattern.
In this method, a mask pattern may also be formed over the upper silicon layer. In this case, the hole is formed in the upper silicon pattern and the porous silicon pattern by sequentially etching the upper silicon layer and the porous silicon layer using the mask pattern as a mask.
In the forming of the isolating insulation layer, an insulation layer may be formed over the upper silicon pattern and in the reverse T-type hole. This insulation layer is then subsequently planarized by etching, at which time the mask pattern is simultaneously removed.
In the forming of the porous silicon layer, an impurity-containing silicon layer may be formed over the lower silicon substrate, and silicon can then be extracted from the impurity-containing silicon layer.
In this method, a thermal oxide layer may be formed over an entire exposed surface in the reverse T-type hole. Also, an air layer may be formed in the isolating insulation layer under the upper silicon pattern adjacent to the undercut porous silicon layer.
The undercut porous silicon pattern may be obtained by isotropically etching the porous silicon pattern.
According to another aspect of the present invention, another method is provided for manufacturing a semiconductor device having an SOI structure. In this method, a porous silicon layer is formed in a lower silicon substrate to define a first region of the lower silicon substrate. An upper silicon layer is then formed over the porous silicon layer and the lower silicon substrate. A hole is then formed in the upper silicon layer and the porous silicon layer to expose a second region of the lower silicon substrate and to define an upper silicon pattern and a porous silicon pattern. A reverse T-type hole is formed by removing the porous silicon pattern, and at the same time partially electrically contacting the lower silicon substrate and the upper silicon pattern through the first region of the lower silicon substrate. The lower silicon substrate is partially electrically isolated from the upper silicon pattern by forming an isolating insulation layer in the reverse

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