Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-11-30
2003-07-22
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S423000, C438S440000, C438S528000
Reexamination Certificate
active
06596593
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a field effect semiconductor device having a MOS structure and a method of manufacturing the same.
The present invention relates to a semiconductor device forming a semiconductor integrated circuit such as a voltage regulator, a switching regulator, or a voltage detector that is used for controlling power supply voltage in a portable device or the like, and to a method of manufacturing the same. The present invention also relates to a semiconductor integrated circuit device into and from which plural levels of voltages are inputted and outputted, and to a method of manufacturing the same.
2. Description of the Related Art
Conventionally, plural levels of power supply voltages are applied to or plural levels of output voltages are outputted from one semiconductor device. In this case, it is required to form different semiconductor devices having different processes on one substrate. Hence, in the semiconductor device, its device configuration and process flow are complicated and the number of elements to be controlled and that of manufacturing steps increase. This has caused detrimental effects, for example, increases in production turn around time (TAT) and in production cost.
It has been well-known that in order to eliminate such detrimental effects, a manufacturing method is employed in which a dual-gate is used, a channel stopper is applied to a high-voltage element, or the like.
This manufacturing method is described with reference to drawings as follows.
FIGS. 9
to
11
are schematic sectional views illustrating a conventional method of manufacturing a semiconductor device in the manufacturing step order.
P wells
2
and N wells
16
are formed in the vicinity of the surface of a P-type semiconductor substrate
1
(hereinafter referred to as “Psub
1
”) by a photo process, an ion implantation process, and a thermal diffusion process. Afterward, thick oxide films
19
for element isolation, N-type channel stoppers
15
, and P-type channel stoppers
14
are formed by a LOCOS method, an ion implantation process, a photo process, and the like. Thin oxide films
20
are formed by utilizing thermal oxidation. Photoresists
5
are formed on channel regions in regions to be high-voltage drive elements later, and the thin oxide films located in the other regions are removed by wet etching. Thus, the configuration shown in
FIG. 9
is obtained.
Subsequently, the photoresists
5
are removed and then thick gate oxide films
22
for high voltage and thin gate oxide films
23
for low voltage are formed by utilizing thermal oxidation again. Thus, the configuration shown in
FIG. 10
is obtained.
In this case, the thickness of the gate oxide films is set so that the electric field applied to the gate oxide films does not exceed 4 MV/cm.
Next, Poly-Si gates
3
are formed by a CVD process, a photo process, an etching process, and the like. For respective elements, an N
+
source
11
, an N
+
drain
10
, a P
+
source
18
, and a P
+
drain
17
are formed by a photo process, an ion implantation process, and the like. Thus, the configuration shown in
FIG. 11
is obtained.
Subsequent steps to be carried out are not shown in the drawings, but interlayer insulating films, contact holes, metal wirings, PADs for external connection, and a protective film are formed by ordinary semiconductor manufacturing processes. Thus, a conventional semiconductor device is completed.
In the conventional semiconductor device, however, the channel stoppers formed by the LOCOS method and the ion implantation process are used for the sources and drains in the low-voltage element. Hence, such a conventional semiconductor device had the following problem in structure.
As shown in
FIGS. 9
to
11
, the sources and drains formed by the LOCOS method and the ion implantation process are used for the high-voltage elements
23
and
24
. Hence, there was a disadvantage in that the element size increases due to such a configuration.
Here, the LOCOS method and the ion implantation process are described. Generally, the LOCOS method is a manufacturing method including the steps of: forming nitride films with a high thermal-oxidation-resistant masking characteristic in regions to be active regions later by a photo process and an etching process; forming N-type and P-type impurity regions in regions to be N-type and P-type channel stoppers later, respectively, by a photo process and an ion implantation process; then forming thick oxide films for element isolation and N-type and P-type channel stoppers by thermal oxidation and thermal diffusion (for instance, a thermal oxidation and diffusion process at 1100° C. for about three hours); and forming element isolation regions and the active regions by removing the nitride film and oxide films over the active regions.
As described above, when the N-type and P-type channel stoppers formed by the above-mentioned LOCOS method and the like are used for the sources and drains of the elements for high voltage, reduction in element size is difficult due to such an element configuration. As shown in
FIG. 11
, the thick oxide films
19
that also serve as the element isolation regions are required to be provided on both sides of each thick gate oxide film
22
for high voltage. Consequently, it is difficult to prevent the size of the element including the channel, source, and drain regions from increasing.
Furthermore, in the conventional semiconductor device and the conventional method of manufacturing a semiconductor device, two types of gate oxide films are required in accordance with applied voltages, which leads to the following problem in manufacturing.
As shown in
FIGS. 9
to
11
, since the thermal oxidation process is carried out twice to form the thick gate oxide films
22
for high voltage, their thickness has great variation. The reason for this is described as follows. That is, generally, a hydrogen peroxide solution containing ammonia is used in a washing step carried out prior to the second thermal oxidation step, and this washing liquid etches and removes a part of the oxide film surface when the oxide film surfaces are washed with the liquid. Therefore, the etching amount differs depending on the state of the washing liquid and thus the base oxide films have variations in their thickness before the second thermal oxidation is carried out. As a result, the thick gate oxide films
22
for high voltage have great variations in their thickness. Such variations result in variations in threshold voltage and driving current value of the high-voltage elements, thus deteriorating characteristics of a semiconductor integrated circuit device, and making it difficult to increase accuracy in the characteristics of the semiconductor integrated circuit device.
SUMMARY OF THE INVENTION
In order to solve the above-mentioned problems, according to the present invention, the following means are adopted.
According to the present invention, there is provided a method of manufacturing an insulating-gate-type semiconductor device, the method comprising: a first step of forming a polycrystalline silicon gate in a vicinity of a surface of a P-type semiconductor substrate with a gate insulating film interposed between the polycrystalline silicon gate and the P-type semiconductor substrate; a second step of forming oxygen-ion implanted regions by implantation of oxygen ions into the polycrystalline silicon gate and a region in the vicinity of the surface of the P-type semiconductor substrate; a third step of forming oxide films by high-temperature annealing of the oxygen-ion implanted regions; a fourth step of forming N-type impurity regions through introduction of N-type impurities in a self-alignment manner with respect to a gate electrode formed of the polycrystalline silicon gate; and a fifth step of forming N-type high-concentration impurity regions through introduction of N-type impurities at a distance from the gate electrode.
According to the present invention, there is provide
Adams & Wilks
Chaudhari Chandra
Seiko Instruments Inc.
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