Method of fabricating a flash memory cell

Details Method of fabricating a flash memory cell Method of fabricating a flash memory cell

2001-10-22

2003-07-22

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S589000

Reexamination Certificate

active

06596588

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a split-gate flash memory cell, and more particularly, to a method of fabricating a split-gate flash memory cell utilizing point discharge to reduce an erasing voltage.
2. Description of the Prior Art
Depending on the structure of gate, flash memory can be divided into a stacked-gate flash memory or a split-gate flash memory. The stacked-gate flash memory cell comprises a floating gate, a dielectric layer with an oxide
itride/oxide (ONO) structure, and a controlling gate stacked respectively on a tunneling oxide layer. Wherein, all the vertical sides of the floating gate, the ONO dielectric layer and the controlling gate of the stacked-gate flash memory cell are approximately aligned. Although the stacked-gate flash memory cell occupies less area, an over-erasing problem sometimes occurs. Therefore, the split-gate flash memory cell is currently used to eliminate the over-erasing problem.
Please refer to
FIG. 1
to
FIG. 4
of schematic diagrams of a prior art method of fabricating a split-gate flash memory cell on a semiconductor wafer
10
. As shown in
FIG. 1
, the semiconductor wafer
10
includes a silicon substrate
12
and a tunneling oxide layer
14
positioned on the silicon substrate
12
.
As shown in
FIG. 2
, a photoresist layer
16
is formed on the surface of the tunneling oxide layer
14
followed by performing a photolithographic process to form a plurality of openings in the photoresist layer
16
. The openings define positions for forming doping regions. Subsequently, using the photoresist layer
16
as a hard mask, an ion implantation process is performed to form two doping regions
22
in the silicon substrate
12
. The photoresist layer
16
is then stripped and a rapid thermal processing (RTP) is utilized to activate the dopants in the doping regions
22
. Therein, one of the two doping regions
22
is a source of the split-gate flash memory cell, and the other is a drain of the split-gate flash memory cell. Furthermore, a region of the silicon substrate
12
between the two doping regions
22
is defined as a channel region
20
of the split-gate flash memory cell.
As shown in
FIG. 3
, a low-pressure chemical vapor deposition (LPCVD) process is performed to form a polysilicon layer (not shown) on the surface of the tunneling oxide layer
14
. A photoresist layer
26
is then coated on the polysilicon layer followed by utilizing a photolithographic process to form patterns for forming a floating gate in the photoresist layer
26
. Subsequently, using the patterned photoresist layer
26
as a mask, an anisotropic etching process is performed to remove portions of the polysilicon layer down to the surface of the tunneling oxide layer
14
, forming a floating gate
24
of the split-gate flash memory cell.
After the photoresist layer
26
is stripped, referring to
FIG. 4
, a thermal oxidation is used to form an ONO dielectric layer
28
, consisting of a oxide layer, a silicon nitride layer and a silicon oxide layer, on the floating gate
24
. Following this, an LPCVD is performed to form a polysilicon layer (not shown) on the semiconductor wafer
10
. Another photoresist layer (not shown) is then coated on the polysillicon layer followed by performing photolithographic and etching processes to define patterns for forming a controlling gate and to remove a portion of the polysilicon layer, thereby forming a controlling gate
30
of the split-gate flash memory cell.
While performing a programming operation of the flash memory cell, effects of channel hot electrons (CHE) are most often utilized at the present time. In this case, the controlling gate
30
is supplied with a high voltage, the source is grounded, and the drain is supplied with a constant voltage. As a result, channel hot electrons occur to penetrate through the tunneling oxide layer
14
and inject to the floating gate
24
, so as to achieve data storage. While performing erasing of the flash memory cell, a Fowler Nordheim tunneling technique is utilized. The controlling gate
30
is grounded or negative biased, and the drain is in a high-voltage state. As a result, the electrons storing in the floating gate
24
are removed.
An electric field of the tunneling oxide layer
14
must be at least 10 million volts per centimeter (MV/cm) while using the Fowler Nordheim tunneling technique to perform erasing operation. In order to prevent a high voltage from destructing the elements, the thickness of the tunneling oxide layer
14
is decreased to between 80 and 120 angstroms (Å) to achieve the high electric field. However, with the decreasing of the tunneling oxide layer
14
, the flash memory cell may have two serious problems:
(1). Since the tunneling oxide layer
14
is not thick enough to provide the electrons stored in the floating gate
24
with an effective potential barrier, the ability of data retention of the flash memory cell is affected.
(2). A capacitance between the floating gate
24
and the silicon substrate
12
is increased with the decrease of the thickness of the tunneling oxide layer
14
. Since a coupling ratio of the flash memory cell is reduced with the increasing of the capacitance between the floating gate
24
and the silicon substrate
12
, the operation voltage of the flash memory cell still cannot be lowered.
SUMMARY OF INVENTION
It is therefore a primary objective of the present invention to provide a method to increase a thickness of a tunneling oxide layer and improve qualities of a split-gate flash memory cell.
It is another objective of the present invention to provide a method of fabricating a split-gate flash memory cell to lower an erasing voltage.
According to the claimed invention, a V-shape structure is formed in a semiconductor substrate. A first ion implantation process is then performed to form a first doping region around the V-shape structure in the semiconductor substrate. Following this, a first dielectric layer is formed on surfaces of the semiconductor substrate and the first doping region. A floating gate is formed on the first dielectric layer over the first doping region and a second dielectric layer is formed on the floating gate, respectively. A controlling gate is then formed on the second dielectric layer. Finally, a second ion implantation process is performed utilizing the controlling gate as a mask to form a second doping region in the semiconductor substrate.
It is an advantage of the present invention that the V-shape structure is positioned under the floating gate. While using the Fowler Nordheim tunneling technique to erase, point discharge is utilized through the V-shape structure to facilitate removal of the electrons storing in the floating gate. Thus, the erasing voltage of the flash memory cell can be effectively lowered according to the present invention. Additionally, the problems resulting from supplying a high voltage on the controlling gate, as in the prior art, are completely prevented.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.


REFERENCES:
patent: 5591652 (1997-01-01), Matsushita
patent: 5780341 (1998-07-01), Ogura
patent: 6051465 (2000-04-01), Kato et al.
patent: 6051860 (2000-04-01), Odanaka et al.
patent: 6157058 (2000-12-01), Ogura
patent: 6184086 (2001-02-01), Kao
patent: 6372564 (2002-04-01), Lee
patent: 448576 (2001-08-01), None
IBM Techical Disclosure Bulletin NN80055296 May 1, 1980 vol. 22, Issue 12, pp. 5296-5297.

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