Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-22
2003-06-17
Clark, Sheila V. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S261000, C438S151000
Reexamination Certificate
active
06580135
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90114685, filed on Jun. 18, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor memory structure and associated method of programming and erasure. More particularly, the present invention relates to a silicon nitride read only memory (NROM) structure and associated method of programming and erasure.
2. Description of Related Art
Most conventional read only memory employs a channel transistor to serve as the principle component in each memory unit. In the programming stage, dopants are selectively implanted into designated channel region for changing the threshold voltage such that the ‘On’ or ‘Off’ state of a memory transistor is set. The structure of a read only memory includes a word line running perpendicularly across a bit line so that the channel of the memory unit is formed in the region underneath the word line between the bit lines. Whether a binary bit ‘0’ or ‘1’ is stored in a read only memory unit depends on the implantation of ions in the channel.
Following the rapid development of electrically erasable and programmable read only memory (EEPROM), the storage of bit data inside a read only memory unit no longer depends on the implantation of ions into the channel. A type of oxide-nitride-oxide (ONO) EEPROM has an ONO layer formed above the channel area between the bit lines. This ONO layer is capable of isolating the overlapping polysilicon word lines and the silicon nitride layer is capable of trapping electric charges. Hence, data can be programmed into a memory unit with ease.
FIG. 1
is a schematic cross-sectional view showing a conventional silicon nitride read only memory unit. The memory structure includes a substrate
10
, a source region
11
, a drain region
12
, an oxide-nitride-oxide (ONO) composite layer
18
and a polysilicon gate
16
above the layer
18
. The ONO layer
18
is formed over the substrate
10
. The ONO layer
18
actually comprises a silicon nitride layer
14
, a bottom oxide layer
13
and a top oxide layer
15
. Both the source region
11
and the drain region
12
are formed within the substrate
10
on each side of the ONO structure
18
. A channel region
17
is formed underneath the ONO structure
18
between the source region
11
and the drain region
12
.
In a conventional semiconductor transistor, the source terminal, the drain terminal and the gate terminal generally are doped identically, for example, p-doped or n-doped. As shown in
FIG. 1
, N-type ions are implanted into the source region
11
, the drain region
12
and the gate region
16
so that these regions are all in the n-doped state.
The silicon nitride layer
14
inside the ONO composite structure
18
has the capacity for trapping electric charges. In memory programming, suitably programmed voltages are applied to the source terminal
11
, the drain terminal
12
and the gate terminal
16
respectively. Electrons in the source terminal
11
move into the channel
17
and flow towards the drain terminal
12
. During the electron flow, a portion of the electrons may penetrate the bottom oxide layer
13
and halt within the silicon nitride layer
14
. Such a penetration of electrons through the bottom oxide layer
13
into the silicon nitride layer
14
is often referred to as a tunneling effect.
There are two major conditions in which tunneling occurs. One type of tunneling is referred to as a channel hot electron injection while the other type of tunneling is referred to as Fowler-Nordheim tunneling.
FIG. 2
is a schematic cross-sectional view showing hot electron injection inside a conventional nitride read only memory. As shown in
FIG. 2
, a positive voltage is applied to the gate terminal
26
so that the channel
27
is opened. When a relatively large bias voltage is applied between the source terminal
21
and the drain terminal
22
, a large number of excess hot electrons
29
is generated inside the channel
27
. A portion of the hot electrons
29
penetrates the bottom oxide layer
23
. Through the edges of the bottom oxide layer
23
, electrons move into the silicon nitride layer
24
. Such a transfer of electrons into the silicon nitride layer
24
is also known as hot electron injection. To remove the electrons
29
within the silicon nitride layer
24
, a negative voltage is applied to the gate terminal
26
so that electrons
29
can penetrate through the bottom oxide layer
23
and channel into the drain terminal
22
. This is a reverse operation of the hot electron injection and is often called negative gate drain erase (NGDE).
FIG. 3
is a schematic diagram showing a FN tunneling of electrons into a silicon nitride layer inside a conventional silicon read only memory. As shown in
FIG. 3
, when a bias voltage is applied to the source terminal
31
and the drain terminal
32
, a positive voltage applied to the gate terminal
36
opens up the channel
37
. Hence, electrons
39
are able to pass through the channel
37
. If a relatively large positive voltage is applied to the gate terminal
36
, electrons
39
within the channel
37
penetrate through the bottom oxide layer
33
into the silicon nitride layer
34
. This is the so-called FN tunneling effect. On the other hand, to drive the electrons
39
trapped within the silicon nitride layer
34
away, a relatively large negative voltage is applied to the gate terminal
36
. The trapped electrons
39
within the silicon nitride layer
34
penetrate through the bottom oxide layer
33
into the channel
37
. This is a reverse operation of the FN tunneling often called the negative gate channel erase (NGCE).
Conventionally, the programming and erasing of data in a silicon nitride read only memory can have two different modes. In the first operating mode, electrons are induced into the silicon nitride layer via FN tunneling while trapped electrons are driven off by negative gate channel erase (NGCE). In the second operating mode, electrons are induced into the silicon nitride layer via hot electron injection while trapped electrons are driven off by negative gate drain erase (NGDE).
Because the doped ions in the gate conductive layer and the doped ions in the channel are in opposite states, differences in energy levels between the two layers are relatively large. Hence, if electrons are collected via FN tunneling, a rather large operating voltage must be applied to the gate terminal. Therefore, the tunneling oxide layer (or the bottom oxide layer) must have high reliability. Conversely, to remove trapped electrons by negative gate drain erase, electrons within the silicon nitride layer are held back strongly due to the great energy gap between the material layers. The application of a negative voltage at the gate terminal leads to a portion of the hot holes penetrating the bottom oxide layer into the silicon nitride layer, thereby erasing some of the electrons within the silicon nitride layer. However, the movement of hot holes from the bottom oxide layer may seriously damage the structure of the bottom oxide layer and degrade the isolating property of the oxide layer. Ultimately, overall reliability of the semiconductor memory device deteriorates.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a silicon nitride read only memory and associated programming and erasing method. The silicon nitride read only memory has identically ion doped gate conductive layer and channel so that the energy gap between the two layers is brought closer together. Ultimately, operating voltage at the gate terminal is reduced and damage to the tunnel oxide layer by hot holes is prevented.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a silicon nitride read only memory. The read only memory includes a first type ion-doped semiconductor substrate, an oxide-nitride-oxide (ONO) composite layer over the semicond
Chen Chia-Hsing
Chou Ming-Hung
Hwang Jiunn-Ren
Liu Cheng-Jye
Clark Sheila V.
J. C. Patents
Macronix International Co. Ltd.
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