Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-09-24
2003-06-24
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S002000
Reexamination Certificate
active
06584596
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to the field of integrated circuit design; more specifically, it relates to a method for designing a voltage partitioned solder-bump package.
In an effort to increase performance, lower power consumption and integrate several integrated circuit technologies on the same chip, the concept of voltage islands has been introduced into integrated circuit design.
The voltage island concept allows for one or more regions of an integrated chip (islands) to be powered by both a chip wide power source (VDD) and one or more additional, voltage island power sources (VDDX.) VDDX and VDD can be switched on and off by the user as the operation of the integrated circuit demands. However, integrated circuit chips are generally mounted to a next higher level of packaging. One widely used class of packages is solder-bump packages. Solder bump packages derive their name from the fact that integrated circuit chips are attached to pads on the package with solder bumps. Solder bump connections are also known as C4 (controlled collapse chip connections.)
A solder bump package for an integrated circuit chip having a voltage island (a voltage partitioned solder-bump package) must be compatible with and capable of supporting the power distribution and noise requirements of the voltage island, while not violating the geometric constraints of the solder-bump package technology. Such restraints include, for example, placement of package voltage island power planes to be under the solder bumps to provide low inductance, thus restricting which and how many package pins may be assigned to a particular voltage island. Additionally, the presence of power and signal planes in the package substrate must be accounted for.
Present design methodology for voltage partitioned solder-bump packages relies heavily on user intervention and trial and error approaches that are both costly and time consuming. An automated design methodology for voltage partitioned solder-bump packages would greatly speed up the solder-bump package design process and reduce costs.
SUMMARY OF THE INVENTION
A first aspect of the present invention is a method of designing voltage partitions in a solder bump package for a chip, comprising: determining the current requirements of a chip voltage island, the chip voltage island including chip power and signal pads, and creating an equivalent circuit model of the chip voltage island; defining a package voltage island, the package voltage island including power and signal package pins, and creating an equivalent circuit model of the package voltage island; analyzing electrical attributes of a combination of the chip voltage island model and the package voltage island model; and modifying the package voltage island until the electrical attributes are acceptable.
A second aspect of the present invention is a computer system comprising a processor, an address/data bus coupled to the processor, and a computer-readable memory unit coupled to communicate with the processor, the memory unit containing instructions that when executed implement a method for designing voltage partitions in a package for a chip, the method comprising the computer implemented steps of: determining the current requirements of a chip voltage island, the chip voltage island including chip power and signal pads, and creating an equivalent circuit model of the chip voltage island; defining a package voltage island, the package voltage island including power and signal package pins, and creating an equivalent circuit model of the package voltage island; analyzing electrical attributes of a combination of the chip voltage island model and the package voltage island model; and modifying the package voltage island until the electrical attributes are acceptable.
A third aspect of the present invention is a program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for designing voltage partitions in a package for a chip the method steps comprising: determining the current requirements of a chip voltage island, the chip voltage island including chip power and signal pads, and creating an equivalent circuit model of the chip voltage island; defining a package voltage island, the package voltage island including power and signal package pins, and creating an equivalent circuit model of the package voltage island; analyzing electrical attributes of a combination of the chip voltage island model and the package voltage island model; and modifying the package voltage island until the electrical attributes are acceptable.
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Buffet et al., “Methodology for I/O Cell Placement and Checking in ASIC Designs Using Area-Array Power Grid,” IEEE 2000 Custom Ics Conference, pp. 125-128.
Buffet Patrick H.
Chiu Charles S.
Sun Yu H.
Garbowski Leigh M.
International Business Machines - Corporation
Kotulak Richard M.
Schmeiser Olsen & Watts
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