Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1998-05-07
2003-08-12
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S706000, C438S717000, C438S725000
Reexamination Certificate
active
06605541
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a method of manufacturing a high performance semiconductor device. More specifically, this invention relates to a method of manufacturing a high performance semiconductor device with features having a pitch of ½ the minimum pitch achievable in the manufacturing process being utilized. Even more specifically, this invention relates to a method of manufacturing a high performance semiconductor device with features having a pitch of ½ the minimum pitch achievable in the manufacturing process being utilized by using an offset mask with the minimum pitch.
2. Discussion of the Related Art
Industry and consumer demands for improved high performance products containing semiconductor devices are increasing at a high rate. The increased demands for improved high performance products are being met by improving performance of the electrical circuitry and by increasing the speed at which the semiconductor devices function. A result of increasing the performance of the increased electrical circuitry and increasing the speed is that it is necessary to manufacture more and more transistors into a fixed area of silicon. The performance of a semiconductor device, such as a microprocessor, is related to several factors, one of which is the width of the polysilicon gates of the FET transistors that are formed on the device.
In the leading state of the art process technologies, there have been attempts to reduce the final gate dimension and other feature dimensions. Some of these attempts include a process of over-exposing the photoresist mask and trimming the resist and hard masks. Some of the attempted methods have resulted in limited success, however, the methods are difficult to control and show varying results. However, these methods only reduce the main feature width while the overall spacing of the feature increases. Because the pitch of the device does not decrease, there is no gain in density. The ultimate limiting factor is that the parameters of a manufacturing process limit the achievable minimum pitch. Some of the limiting factors are the parameters of the lithographic system being used to manufacture the semiconductor device. For example, a limiting factor is the wavelength of the radiation utilized to illuminate the mask or reticule in order to transfer the pattern on the reticule to the wafer being manufactured. Another limiting factors of the lithographic system is the quality of the lens system that reduces the size of the pattern on the reticule to the size that is imaged onto the wafer. In order to improve the lithographic systems, various steps have been undertaken such as reducing the wavelength of the illuminating radiation. Currently, ultraviolet sources are used, however, the lens materials available that will efficiently transmit ultraviolet radiation are limited and those that are available are very expensive. Other radiation sources, such as x-ray sources have been proposed as well as electron-beam lithography systems. These alternative sources have the potential to further decrease the feature size of the resulting semiconductor device, however, the systems utilizing the x-ray or electron-beam sources have problems.
An example of the current technology utilizing a deep ultra violet (DUV) for the quarter micro process technology uses a source of radiation having a wavelength of 248 nanometers. To insure the printed minimum feature having an acceptable depth of focus, the printed feature is usually targeted slightly larger than the wavelength. In this case, the printed feature is targeted at 260 nanometers.
Therefore, what is needed is a method of manufacturing a semiconductor device. utilizing the currently available lithographic systems that can provide features substantially less than, for example, the targeted 260 nanometers when the illumination source has a wavelength of 248 nanometers.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other advantages are attained by a method of manufacturing a semiconductor device that will have features with a dimension of ½ the minimum pitch that is determined by the parameters of the manufacturing process. In accordance with the present invention, a target layer of material that is to have dimensions of ½ the minimum pitch is formed on a partially completed semiconductor device. The target layer of material is subjected to a first etch process with masks having a dimension of the minimum pitch. The target layer of material is then subjected to a second etch process with the masks offset by a distance of ½ the minimum pitch.
The first etch process includes forming a hard mask layer on the target layer, etching the hard mask layer using a first photoresist pattern having dimensions of the minimum pitch which exposes portions of the target layer having dimensions of the minimum pitch. The first photoresist pattern is removed and the hard mask layer and the portions of the exposed target layer are etched using a second photoresist pattern having dimensions of the minimum pitch. The second photoresist is offset from the position of the first photoresist pattern by ½ the minimum pitch.
The second etch process includes removing the second photoresist layer, forming a film having a high etch selectivity with respect to the hard mask, removing the remaining portions of the hard mask layer which exposes the further portions of the target layer. The further portions of the target layer are etched resulting in the target layer having dimensions of ½ the minimum pitch.
The method of manufacturing of the present invention thus provides a method of obtaining a structure that has dimensions of ½ the minimum pitch achievable by a particular manufacturing process. The method of the present invention thus extends the usefulness of current manufacturing processes that have been limited by parameters of the manufacturing processes.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 4414057 (1983-11-01), Bourassa et al.
patent: 4484978 (1984-11-01), Keyser
patent: 5201993 (1993-04-01), Langley
patent: 5346586 (1994-09-01), Keller
patent: 5444020 (1995-08-01), Lee et al.
Deo Duy-Vu
Utech Benjamin L.
LandOfFree
Pitch reduction using a set of offset masks does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pitch reduction using a set of offset masks, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pitch reduction using a set of offset masks will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3095616