Method of forming metal interconnection using plating and...

Details Method of forming metal interconnection using plating and... Method of forming metal interconnection using plating and...

2000-09-14

2003-08-26

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S645000, C438S648000, C438S650000, C438S654000, C438S678000, C438S679000, C438S680000, C438S687000, C438S691000, C438S692000, C438S653000, C257S751000, C257S752000, C257S753000, C257S762000

Reexamination Certificate

active

06610596

ABSTRACT:

This application relies for priority upon Korean Patent Application Nos. 99-39548 and 00-42153, filed on Sep. 15, 1999, and Jul. 22, 2000, respectively, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a method of forming a metal interconnection using plating and a semiconductor device manufactured by the method. More particularly, the present invention relates to a method for manufacturing a metal interconnection in a semiconductor device having a damascene structure and a semiconductor device manufactured by such a method.
In order to reduce RC delay time in a semiconductor device, a method has been studied of forming a metal interconnection layer using metal such as copper, which has a low resistivity. A reduction in RC delay time is particularly useful in logic devices that require a high operation speed.
In one method of forming a metal interconnection material, a metal interconnection material, such as aluminum, is formed over the entire surface of a substrate and the resultant structure is patterned by a conventional photolithography process. However, a different method is used when forming a metal interconnection layer with copper (Cu) as a metal interconnection material because it is difficult to perform a patterning process with respect to copper. In order to form a metal interconnection layer using this process, a region where a metal interconnection is to be made is formed in an insulation layer on a substrate in advance, and then this area is filled with a metal interconnection material. A so-called “damascene” process is used to achieve this method.
FIGS. 1 through 3
are sectional views for explaining a method of forming a metal interconnection of a semiconductor device having a conventional line damascene structure. In the line damascene structure, a trench having a predetermined depth from the surface of an insulation layer is formed in a line and a metal interconnection layer is formed in the trench. A method of forming a metal interconnection of a line damascene structure will now be described with reference to the attached drawings.
Referring to
FIG. 1
, a trench region
11
of a line shape is formed by performing a photolithography process on an insulation layer
10
, which is formed over a substrate
5
. Subsequently, a diffusion prevention layer
12
is formed over the entire surface of the insulation layer
10
, including the trench region
11
. Next, copper is deposited over the diffusion prevention layer
12
by a physical vapor deposition (PVD) method such as sputtering, thereby forming a seed layer
14
.
Referring to
FIG. 2
, a plating layer
16
of copper is then formed over the resultant structure, including the seed layer
14
, using an electroplating method. The plating layer
16
is formed thick enough to completely fill the trench region
11
.
Referring to
FIG. 3
, some of the plating layer
16
is then removed by a chemical-mechanical polishing (CMP) process until a portion of the insulation layer
10
is exposed. As a result of this, remaining portions of the diffusion prevention layer
12
and the seed layer
14
, as well as a metal interconnection layer
16
a
that is formed from the portion of the plating layer
16
remains within each trench region
11
, in the vicinity of the surface of the insulation layer
10
.
FIGS. 4 through 7
are a plan view and section views for explaining a method of forming a metal interconnection of a semiconductor device having a conventional dual damascene structure. In the dual damascene structure, a metal interconnection formed to fill a trench region of a line shape is combined with a contact filling a contact hole or a via-hole in order to connect to an underlying conductive layer. A method of forming a metal interconnection of a dual damascene structure will be described below.
Referring to
FIG. 4
, lower conductive layers
28
are formed over a substrate
5
at a predetermined interval. Metal interconnection layers
26
a
are formed over the lower conductive layers
28
at another predetermined interval. An insulation layer (not shown in
FIG. 4
) is interposed between the metal interconnection layer
26
a
and the underlying lower conductive layer
28
. The metal interconnection layer
26
a
is electrically connected to the underlying lower conductive layer
28
through a contact hole region
30
.
FIGS. 5 through 7
are sectional views of
FIG. 4
taken along the line VII-VII′, and show the sequential steps of fabricating the device of FIG.
4
.
Referring to
FIG. 5
, a conductive material is deposited and patterned over a substrate
15
to form lower conductive layers
28
at regular intervals. Subsequently, an insulation layer
20
is formed over the entire surface of the resultant structure, including the lower conductive layers
28
. A typical photolithography process is then performed on the insulation layer
20
to form a contact hole region
30
and a trench region
31
that includes the contact hole region
30
. Next, a diffusion prevention layer
22
and a seed layer
24
are sequentially formed over the entire surface of the resultant structure, including the contact hole region
30
and the trench region
31
.
Referring to
FIG. 6
, the substrate
15
over which the seed layer
24
is formed is then loaded into an electroplating apparatus and is electroplated to form a plating layer
26
of copper.
Referring to
FIG. 7
, the surface of the substrate
15
, including the plating layer
26
, is then planarized by a chemical mechanical polishing (CMP) process. This surface polarization is performed on the plating layer
26
, the seed layer
24
, and the diffusion prevention layer
22
until the surface of the insulation layer
20
is exposed. In this way a metal interconnection layer
26
a
is formed that has a dual damascene structure and a planarized surface, as shown in FIG.
7
.
However, the method described above of forming a metal interconnection having a line or dual damascene structure has several problems. First, copper must be thickly deposited to make certain that enough copper is deposited to form a layer that fills the trench region
31
and has at least a predetermined thickness over the insulation layer
24
, taking into account the depth of the trench region
31
and contact hole region
30
, and the parameters of the chemical mechanical polishing (CMP) process. Thus, the amount of copper subject to the polishing is large. This decreases the throughput of the fabrication process decreases, and increases fabrication expense.
Second, as the amount of copper subject to the polishing increases, the uniformity of the chemical mechanical polishing (CMP) process is degraded. This causes the thickness of a metal interconnection layer
26
a
finally formed in a substrate
15
to vary according to its location, which directly affects the reliability and throughput of the devices.
Third, when removing the copper layer using the chemical mechanical polishing (CMP) process, corrosion of the insulation layer
24
occurs according to the density of a metal interconnection layer pattern. This also causes the thicknesses of the metal interconnection layers
26
a
in a substrate
15
to vary, which, as noted above, results in defects.
Fourth, different slurries must be used when polishing a seed layer
24
and a diffusion prevention layer
22
when the seed layer
24
and the diffusion prevention layer
22
have different polishing speeds. This complicates the chemical mechanical polishing (CMP) process and increases fabrication expense.
Fifth, in a dual damascene structure, the aspect ratio of a contact hole region
30
is very large, which may result in the formation of a void
32
during electroplating, as shown in FIG.
6
. Such a void
32
, as shown in
FIG. 7
, remains as a void defect
32
a
on the surface of the metal interconnection layer
26
a
after surface polarization, thereby deteriorating the reliability of the resulting devices.
SUMMARY OF THE INVENTION
It is a first objective of

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