Method for etching low k dielectrics

Details Method for etching low k dielectrics Method for etching low k dielectrics

2000-07-05

2003-04-15

Ryan, Patrick (Department: 1745)

Etching a substrate: processes

Gas phase etching of substrate

Etching a multiple layered substrate where the etching...

C216S067000, C216S074000, C216S079000, C216S081000, C438S735000, C438S743000

Reexamination Certificate

active

06547977

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a method of etching low “k” dielectric materials. The method may be used for patterned etching or for etchback applications. The method is particularly useful for etching low k materials comprising at least about 80 percent by weight of a polymeric material. Typically, the polymeric material is an organic based material. In addition, the method may be used for the etching of low k materials having an inorganic constituent which is susceptible to a plasma comprising chlorine and oxygen species.
2. Brief Description of the Background Art
In the field of semiconductor device fabrication, it is well recognized that as device feature sizes decrease to 0.18&mgr; and smaller, RC delay of interconnects becomes a major limiting factor for device speed. There are two areas of development focusing on this problem. The interconnect conductor resistance is being reduced by the use of copper and other conductors having a lower resistance (R) than aluminum, which has been the industry standard for conductive interconnect material. The second area of focus is the use of a dielectric material having a lower dielectric constant (k) than silicon dioxide, which has been the industry standard dielectric. Presence of a lower k dielectric reduces the interconnect contribution to the capacitance (C).
There are two alternate technologies which are used in the formation of semiconductor interconnect structures. The first technology is known as damascene technology. In this technology, a typical process for producing a multilevel structure using copper as the conductive material for feature sizes in the range of 0.25 micron (&mgr;m) or less would include: blanket deposition of a dielectric material; patterning of the dielectric material to form openings; deposition of a diffusion barrier layer and, typically, a wetting layer to line the openings; deposition of a copper layer onto the substrate in sufficient thickness to fill the openings; and removal of excessive conductive material from the substrate surface using chemical-mechanical polishing (CMP) techniques. The method requires a patterned etching of the dielectric material. The damascene process is described in detail by C. Steinbruchel in “Patterning of copper for multilevel metallization: reactive ion etching and chemical-mechanical polishing”,
Applied Surface Science
91 (1995) 139-146.
The competing technology is one which involves the patterned etch of the conductive copper layer. In this technology, a typical process would include deposition of a copper layer on a desired substrate (typically a dielectric material having a barrier layer on its surface); application of a hard masking material and a photoresist over the copper layer; pattern etching of the photoresist, hard masking material, and copper layer using wet or dry etch techniques; and deposition of a dielectric material over the surface of the patterned copper layer, to provide isolation of conductive lines and contacts which comprise various integrated circuits. Subsequent to application of the dielectric material, it is typically necessary to etch back the dielectric material to expose contact points on the conductive lines and contacts.
U.S. Pat. No. 5,591,677, issued to Shin-Pun Jeng in January of 1997, describes a multi-level interconnect structure having embedded low-dielectric constant insulators, and a method for making the structures. In particular, the dielectric portion of the structure includes layers of low dielectric constant organic polymers used in combination with layers of silicon dioxide. The patent describes the problems inherent in using organic polymers as dielectrics, due to thermal stability problems and etching difficulties. However, the inventor has developed a method of etching back the organic low k dielectric material to expose the upper surface of a plurality of interconnect lines. In particular, the etching is carried out using an oxygen plasma etch with a small amount of CF
4
present. Low k dielectrics which are recommended for use in the method are the polytetrafluoroethylene “Teflon” (a trademark of Du Pont Corporation); benzocyclobutene (BCB); parylene; polyimide; or other material having a dielectric constant less than 3.9. Parylene is used in the preferred embodiment.
U.S. Pat. No. 5,565,384 to Havemann, issued Oct. 15, 1996, describes a self-aligned via using low permittivity dielectric. The low permittivity dielectric is used to reduce capacitance between adjacent conductors on a connection layer. The method of fabricating the via includes the filling of horizontal gaps between patterned conductors with an organic-containing dielectric material (Allied Signal 500 Series), forming an inorganic dielectric layer over the organic-containing dielectric material, and using a high density plasma comprising fluorocarbons to etch the silicon dioxide while not appreciably etching the organic-containing dielectric material. The organic-containing material reduces the device capacitance while acting as an etch stop, preventing overetching due to either misalignment between the vias and the patterned conductors, or uneven topography across the semiconductor device. The majority of the interlayer dielectric is constructed from oxide or other common dielectrics which possess good heat transfer and structural characteristics.
U.S. Pat. No. 5,679,608 to Cheung et al., issued Oct. 21, 1997, discloses the use of a low dielectric constant material, such as benzocyclobutene or a derivative thereof, as a spin on dielectric over a metal interconnect. In particular, a low dielectric constant material is defined as one having a dielectric constant which is less than that of silicon dioxide (less than about 4.0).
PCT application No. PCT/DE96/02108 of Lauterbach et al. describes a vertically integrated semiconductor component in which the component planes are produced on different substrates and connected by a connection layer of benzocyclobutene. Various organic-comprising layers are said to be plasma etched using a plasma comprising CF
4
/O
2
plasma.
German patent application number DE 4434891 Al, of Lauterbach, published on Sep. 29, 1994, describes the use of bisbenzocyclobutene as a spin on dielectric which can be etched back to expose a conductive element using a CF
4
-based plasma.
Inorganic low k dielectric materials for use in multi-layered circuits for high density semiconductor applications are also known. Generally such materials comprise lead-free amorphous borosilicate glass.
The plasma etching processes described above have included the presence of a fluorine-containing component in the plasma source gas. However, the use of fluorine-comprising etchants is harmful to the environment. Further, when fluorocarbon etchants are used, there is typically a large amount of polymer deposition on device surfaces. In some applications, there is a silicon dioxide layer (or other layer which is readily etched by fluorine) underlying the low k dielectric material. If fluorine is used to etch the low k dielectric, the etch selectivity for the low k dielectric over an adjacent underlying layer may not be acceptable. For example, by the time the low k dielectric layer is etched, an underlying hard mask (such as silicon dioxide and silicon nitride) may be gone. Further, the presence of residual etch process fluorine on the surface of the etched low k dielectric film in an amount which exceeds about 5 atomic % of the film surface composition creates problems in subsequent process integration.
It would be highly advantageous to have a method for etching organic-based (and in some instances inorganic) low k dielectric materials which employs a chemistry which does not suffer from the deficiencies described above with reference to the fluorine-comprising plasma etchants. Preferably the etch chemistry is suitable for etching a number of different kinds of low k materials; exhibits a high etch rate (greater than about 8,000 Å/min); exhibits high selectivity for the low k material relat

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