Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-09-13
2003-08-26
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S266000, C438S954000
Reexamination Certificate
active
06610570
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor device structure and a method of manufacturing the structure. More particularly, the present invention relates to a double-bit non-volatile memory (NVM) structure and a method of manufacturing the structure.
2. Description of Related Art
Non-volatile memory (NVM) is a type of fast access, miniature, power-saving, vibration-resistant and permanent storage media. Thus, the applications of NVM are wide. A prominent type of NVM is the flash memory. One prominent feature of the flash memory is the capacity for block-by-block data erasure so that time is saved.
FIG. 1
is a schematic cross-sectional view showing the structure of a conventional non-volatile memory cell. As shown in
FIG. 1
, the non-volatile memory cell includes a stacked gate structure
110
over a substrate
100
with a source/drain region
120
in the substrate
100
on each side of the stacked gate structure
110
. The stacked gate structure
110
further includes, from bottom to top, a tunnel oxide layer
112
, a floating gate
114
, an inter-gate dielectric layer
116
and a control gate
118
. During programming, electrons are injected into the floating gate
114
. To erase data, a high negative bias voltage is applied to the control gate
118
and hence electrons are channeled away from the floating gate
114
.
However, in order to remove all electrons from the floating gate
114
, over-erasure of the aforementioned non-volatile memory cell often occurs. In other words, too many electrons may be forced out of the floating gate
114
during erasure and result in the accumulation of positive charges in the floating gate
114
In the presence of excess positive charges, an inversion of the channel underneath the floating gate
114
may occur and ultimately may lead to the channel being permanently open and possible data read errors.
To resolve the issue, a split gate structure has been developed.
FIG. 2
is a schematic cross-sectional view of a non-volatile cell having a conventional split-gate structure. As shown in
FIG. 2
, a split-gate structure
210
is formed over a substrate
200
with a source/drain region
220
in the substrate
200
on each side of the split gate structure
210
. The split-gate structure
210
includes, from bottom to top, a tunnel oxide layer
212
, a floating gate
214
, an inter-gate dielectric layer
216
, a control gate
218
and a transfer gate
218
a
. The transfer gate
218
a
extends from the control gate
218
to the side of the floating gate
214
. In this type of design, the channel under the transfer fate
218
a
is open up only when a voltage is applied to the control gate
218
and the transfer gate
218
a
. Hence, even if the channel underneath the floating gate
214
is opened due to over-erasure, the two source/drain regions
220
of the memory cell are still in a non-conductive state, thereby preventing data errors.
Although the split-gate structure
210
is able to prevent data errors due to over-erasure, the design has an adverse effect on miniaturization. This is because the transfer gate
218
a
requires extra area. In addition, the combined widths of the control gate
218
and the transfer gate
218
a
inside the split-gate structure
210
are different from that of the floating gate
214
. The floating gate
214
and the control gate
218
/the transfer gate
218
a
pair must be patterned by applying a photolithographic process twice. Consequently, errors in the overlapping area between the floating gate
214
and control gate
218
/transfer gate
218
a
pair may occur leading to possible non-uniform memory cell properties. Ultimately, electrical performance of each memory cell may be different and may result in some difficulties in controlling the memory cells.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a double-bit non-volatile memory structure having a configuration similar to a flash memory. Each bit of the memory requires an area smaller than a split-gate design and the structure is capable of preventing over-erasure. The structure includes a substrate, a plurality of isolation layers, a plurality of bit lines, a plurality of stacked gate structures, a plurality of doped regions, a plurality of source/drain regions and a plurality of word lines. The isolations layers are formed over the substrate parallel to each other. The bit lines run in a direction perpendicular to the isolation layers and enclose a grid-like unit array. The connecting line between a pair of stacked gate structures within each grid-like unit array is parallel to the isolation layers. Each stacked gate structure includes a floating gate and a control gate above the floating gate. Each doped region is formed in the substrate in the area between neighboring stacked gate structures within a grid-like unit. The source/drain regions are formed in the substrate in areas between neighboring grid-like unit. The source/drain regions and the doped regions are doped identically. The word lines are formed above the stacked gate structures and perpendicular to the bit lines. The two control gates within each grid-like unit are connected electrically to a word line on each side, respectively.
This invention also provides a method of manufacturing a double-bit non-volatile memory having the structure according to this invention. First, isolation layers are formed over a substrate and then a multi-layered structure is formed over the substrate. The multi-layered structure includes, from bottom to top, a tunnel layer, a first conductive layer, an inter-gate dielectric layer and a second conductive layer. The multi-layered structure is patterned to form a plurality of linear multi-layered strips running in a direction perpendicular to the isolation layers. Furthermore, each pair of neighboring linear multi-layered strips defines a linear unit. Source/drain regions and bit lines are formed in the substrate within each linear unit. In addition, a plurality of doped regions is formed between the linear multi-layered strips within each linear unit. The source/drain regions and the doped regions are doped identically. The bit lines and the isolation layers together enclose a plurality of grid-like units. In a subsequent step, various linear multi-layered strips are patterned to form a plurality of stacked gate structures so that each grid-like unit has a pair of stacked gate structures. Each stacked gate structure comprises a floating gate constructed from the first conductive layer and a control gate constructed from the second conductive layer. A plurality of word lines is formed above the stacked gate structures and perpendicular to various bit lines. The pair of control gates inside each grid-like unit is electrically connected to the respective word line on each side.
In the aforementioned method of manufacturing a double-bit non-volatile memory structure, two methods can be used to form the bit lines. One method is to form buried bit lines while the other is to form over the source/drain regions running across the isolation layers.
In addition, the pair of stacked gate structures within a grid-like unit, the doped region between the stacked gate structures of the grid-like unit and the pair of source/drain regions on each side of the grid-like unit together form a memory cell. The control gates of the pair of stacked gate structures within the grid-like unit are electrically connected to the respective word lines on each side of the grid-like unit. The pair of source/drain regions is similarly connected to a pair of neighboring bit lines. Both the source/drain regions and the doped region between the pair of stacked gate structures are doped identically.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5856222 (1999-01-01), Bergemont et al.
patent: 6476439 (2002-11-01), Chen
patent: 6504759 (2
Nhu David
United Microelectronics Corp.
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