Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-23
2003-05-27
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S649000
Reexamination Certificate
active
06569742
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same; and, more particularly, the invention relates to a technique which may be advantageously applied to a system on chip wherein a flash memory (EEPROM: electrically erasable programmable ROM) and a CMOS logic circuit (complementary metal oxide semiconductor logic circuit) are mounted on one chip or to a system wherein a DRAM (dynamic random access memory) and a CMOS logic circuit are mounted on one chip.
BACKGROUND OF THE INVENTION
In the field of advanced technologies such as multi-media and data communication, an effort is recently being put into the development of systems on chip wherein a microcomputer, DRAM, ASIC (application specific integrated circuit), flash memory and the like are mounted on one chip for higher data rates, reduced space requirements (improved packaging density) and lower power consumption.
For example, needs for reduced power consumption in the market have accelerated a trend toward lower voltages. Specifically, the power supply voltage has been reduced from 5 V to 3.3 V. This trend toward low power has opened the door to products of 0.25 micron processing in the field of LSI (large scale integrated circuit) processing techniques, and the main stream of such products is systems which operate on 2.5 V or 1.8 V, interface at a high voltage and operate on a low operating voltage internally.
Referring to device structures, the trend toward higher fineness and higher speeds has spotlighted techniques to achieve lower resistance using a refractory metal silicide film. Especially, the use of a technique for reducing resistance referred to as a “salicide (self-aligned silicide) technique” is effective in providing a system on chip.
The following known articles numbered 1 through 7 disclose salicide techniques.
(1) Japanese laid-open patent publication No. H7-211898 (article 1)
The article 1 discloses a semiconductor device for maintaining the durability of a gate oxide film of a semiconductor device at an I/O portion and a method of manufacturing the same. It also discloses a technique applied to a CMOS, characterized in that a diffusion layer having a concentration lower than that in the source and drain diffusion layers is formed between the source and drain diffusion layers and a gate and in that the low concentration diffusion layer is a non-salicide region unlike the source and drain diffusion regions. The known article 1 will be described later in more detail.
(2) Japanese laid-open patent publication No. H7-106559 (article 2)
The article 2 discloses a method of manufacturing a semiconductor device in which high reliability and cost reduction is achieved by simultaneously forming an insulation film covering the sides of a gate electrode and an insulation film covering the boundary between a device isolating region and a transistor active region. It also discloses a technique for reducing leakage during processing of a side spacer insulation film (silicon oxide film) around a gate by extending a mask up to the end of the device isolating region to leave it, thereby offsetting the source, drain and a silicide film from the device isolating region.
(3) Japanese laid-open patent publication No. H7-183506 (article 3)
The article 3 discloses a transistor having a structure which minimizes both of the layer resistance of a titanium silicide film that constitutes a gate electrode and the layer resistance of a titanium silicide film that constitute source and drain regions having a salicide structure. It also discloses a technique in which a polycrystalline silicon film dominated by (111)-orientation is used as the gate electrode on which the titanium silicide film is formed. That is, the article 1 presents a salicide technique based on the formation of titanium silicide on a gate electrode.
(4) Japanese laid-open patent publication No. H7-263682 (article 4)
The article 4 discloses a method of manufacturing a MISFET having a salicide structure which makes it possible to reduce leakage current and to reduce parasitic resistance.
According to the article 4, a first diffusion layer is formed using ion implantation and a heating process; thereafter, second ion implantation is carried out using side walls as a mask to form a second diffusion layer; and rapid thermal annealing (RTA) is used to activate the impurity in the second diffusion layer. This removes crystal defects in the diffusion layer as a result of the ion implantation and prevents any reduction of the concentration of the impurity in the vicinity of the interface between the surface of the diffusion layer and the bottom of a silicide layer to reduce parasitic resistance.
(5) Japanese laid-open patent publication No. H9-82949 (article 5)
The article 5 discloses a semiconductor device which has less leakage current and an operation speed higher than that in a case wherein neither metal silicide layer nor metal layer is formed on the source and drain regions and a method of manufacturing the same. According to the article 5, an offset layer is formed between the interface of a p-n junction of the source and drain and the end of a metal silicide layer or metal layer in order to suppress the generation of any leakage current between them. The offset layer is controlled by the thickness of a side wall spacer provided on a side wall of the gate (the width of the side wall in the direction of the channel length).
(6) Japanese laid-open patent publication No. H10-12748 (article 6)
The article 6 discloses a CMOS semiconductor device having a structure comprised of different types of gates (dual gate structure) formed by introducing impurities of different conductivity types and discloses the use of a salicide structure and the use of titanium (Ti) or cobalt. (Co) as a specific metallic material to provide the salicide structure.
The following articles disclose techniques for providing a plurality of MISFETs with an LDD (lightly doped drain) structure having various electrical characteristics to be incorporated in one semiconductor substrate.
(7) Japanese laid-open patent publication No. S62-283666 (article 7)
The article 7 discloses a technique in which the width of a side wall is changed to change the width of a semiconductor region having a high impurity concentration located under the side wall. That is, there is provided MISFETs having different offset widths of the regions between the ends of the gate electrodes and the ends of the semiconductor regions having a high impurity concentration. The article 7 does not disclose any application of the salicide technique.
(8) Japanese laid-open patent publication No. S63-226055 (article 8)
The article 8 discloses a technique for maintaining the withstand voltage of an n-channel MISFET and for improving the current driving capability of a p-channel MISFET. According to the technique disclosed in the article 8, the dimensions of an LDD portion of an n-channel MISFET are increased to separate the source and drain regions having a high impurity concentration and to thereby maintain the withstand voltage between those regions, and the dimensions of an LDD portion of a p-channel MISFET are decreased to reduce series resistance of the source region and series resistance of the drain region and to thereby improve current driving capability. This article 8 does not also disclose any application of the salicide technique.
SUMMARY OF THE INVENTION
In a system on chip incorporating a flash memory array and a logic circuit such as a microcomputer, for example, an external power supply of 3.3 V is used which results in a need for a plurality of MISFETs to be driven at the external power supply of 3.3 V, and a first internal power supply voltage of 1.8 V is generated by a voltage reduction circuit for reduced power consumption and increased speed which results in a need for a plurality of MISFETs to be driven at the first internal power supply voltage. Further, a second internal power supply voltage in the range from 10 V to 12 V is generated by a
Hashimoto Takashi
Ikeda Shuji
Kuroda Kenichi
Shukuri Shoji
Taniguchi Yasuhiro
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