Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-03-12
2003-05-27
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S694000, C438S791000, C438S792000
Reexamination Certificate
active
06569768
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacturing of integrated circuits, and particularly to an improved process for forming a capping layer on a copper metallization layer in a semiconductor device.
2. Description of the Related Art
The manufacturing process of modern integrated circuits involves the fabrication of numerous semiconductor devices, such as insulated gate field effect transistors, on a single substrate. To provide increased integration density of the integrated circuits, on the one hand, and, on the other hand, improved device performance, for instance with respect to signal processing time and power consumption, feature sizes of the semiconductor devices are steadily decreasing. The enormous number of semiconductor devices formed on a single chip area, however, reduces the available space for, and hence the cross section of, metallization lines connecting the individual semiconductor devices. As a consequence, the increased electrical resistance of the metallization lines, due to their reduction in size, begins to offset the advantages regarding signal performance of a transistor device that are obtained by reducing the dimensions of a field effect transistor, when a certain amount of reduction of the feature sizes is reached. The electrical resistance of the metallization lines can be reduced in that aluminum, preferably used in modern integrated circuits, is replaced by a conductive material having a lower specific resistance. One candidate for such a low-ohmic material for metallization lines in ultra high-density integrated circuits is copper. Although processing of copper in a semiconductor production line is extremely difficult since the slightest contamination of process equipment not involved in the copper process have an adverse effect on the performance of the final devices, copper is the preferred metallization metal in high end integrated circuits exhibiting feature sizes of 0.2 &mgr;m and beyond. Employing a copper metallization layer in the semiconductor devices, however, gives rise to additional problems, such as corrosion and discoloration, which result in insufficient adhesion to adjacent materials, the consequence being degraded long-time stability of the transistor device. For this reason, after polishing and planarizing the copper metallization layer by means of chemical mechanical polishing (CMP), a reactive plasma treatment is commonly performed to try to remove any copper oxide formed on the copper surface that is exposed by the CMP step. Subsequently, a capping layer, usually a silicon nitride layer, is deposited over the plasma-treated copper metallization layer so as to improve adhesion of the copper to the capping layer to thereby enhance the long-time stability of the metallization layer.
A typical prior art process flow for generating a capping layer over a copper metallization layer may comprise the following process steps. As is well known, after filling openings formed in a dielectric layer with a barrier metal and copper, the excess barrier metal and the excess copper will be removed by a CMP step. The resulting surface of the semiconductor structure obtained by the CMP step comprises surface portions of copper as well as surface portions of the dielectric material, wherein the ratio of exposed copper to dielectric material depends on the type of metallization layer and design rules of the device. As previously mentioned, a subsequent reactive plasma etch step will typically be performed to remove corrosion and discoloration, primarily consisting of copper oxide, formed on the exposed copper surface after the CMP step. To this end, a wafer with the exposed and planarized metallization layer is inserted into a reaction chamber providing a dynamic reactive plasma ambient. The reactive plasma ambient is dynamic in the sense that feed gas is continuously introduced into the chamber and gases are continuously pumped away. Since the plasma etch equipment is well known in the art, a detailed description of a corresponding apparatus will be omitted. For removing copper oxide from the surface of the metallization layer, typically ammonia (NH
3
) gas is continuously fed to the reaction chamber at a predefined flow rate for a predefined time interval while a predefined pressure is maintained in the reaction chamber. Typical process parameters for an according process may be as follows. In a set-up step, approximately 800 sccm ammonia (NH
3
) at a chamber pressure of approximately eight Torr are supplied for approximately fifteen seconds. Subsequently, the high frequency electric field for initiating the plasma is initiated at approximately 200 W for approximately 40 seconds while maintaining the ammonia (NH
3
) flow rate and the pressure in the reaction chamber. Finally, a pump step is carried out for at least 30 seconds to remove reactive gas by-products created during the ammonia (NH
3
) treatment. The duration of the pump step depends on the amount of copper exposed in the metallization layer.
Moreover, typically an in-situ deposition step is carried out to form the capping layer immediately after the ammonia (NH
3
) treatment. For the deposition of the capping layer, in this case silicon nitride, silane gas (SiH
4
) is additionally introduced into the reaction chamber. To control the exposure of the ammonia (NH
3
)-plasma-treated copper surface to silane gas, usually a so-called ramp-up step is carried out in which the flow rate of the silane gas is slowly increased. A typical process flow for the deposition of the silicon nitride layer may comprise the following steps. First, a set-up step of approximately five seconds is carried out with an ammonia (NH
3
) flow rate of approximately 260 sccm and a nitrogen flow rate of approximately 8600 sccm. Thereafter, a ramp-up step of approximately five seconds with a silane flow rate of approximately 50 sccm is performed while maintaining the flow rates for ammonia (NH
3
) and nitrogen. In the following five seconds, the silane flow rate is increased to approximately 100 sccm. In a final ramp-up step of approximately five seconds, the silane flow rate is increased to approiximately 150 sccm and is maintained for a further twelve seconds to deposit the silicon nitride capping layer. Finally, a purge step of approximately ten seconds with nitrogen with a flow rate of approximately 8600 sccm and a subsequent pumping step of about fifteen seconds complete the cycle. According to the process described above, a total time of approximately 142 seconds is required for the ammonia (NH
3
) treatment of the copper surface and the subsequent deposition of the capping layer. With such a process, the silicon nitride capping layer may have a thickness ranging from approximately 300-800 Å.
However, discoloration and corrosion on the copper surface can still be observed when the reaction by-products cannot be effectively removed after the plasma treatment, or when silane is contacting the copper surface in the case when a ramp-up process, in providing the silane gas, is not sufficient to avoid surface reaction of the copper with the reactive ambient. This may occur when design dependent applications of the process described above impose restrictions for the ramp-up step. Moreover, in order to more effectively remove reactive by-products after the plasma treatment, an even longer pump step is required which, on the other hand, significantly reduces throughput.
In view of the above problems, a need exists for an improved process for forming a capping layer on a surface including exposed copper portions.
SUMMARY OF THE INVENTION
According to the present invention, a method of producing a capping layer for a copper surface portion in a semiconductor device is provided, wherein the method comprises providing a substrate having formed thereon a material layer including an exposed surface with a dielectric area and a copper area, creating a dynamic reactive plasma ambient comprising an ammonia (NH
3
) flow, exposing the surface to the reactive plasma ambie
Hohage Joerg
Ngo Minh Van
Ruelke Hartmut
Advanced Micro Devices , Inc.
Guerrero Maria
Williams Morgan & Amerson
Zarabian Amir
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