Electrical computers and digital processing systems: support – Computer power control
Reexamination Certificate
1999-09-10
2003-03-18
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Computer power control
C713S323000, C713S322000, C713S601000
Reexamination Certificate
active
06535982
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a central processing unit and at least one hardware module on a semiconductor chip, and particularly, to a power management device and power management method for reducing the power consumption of the central processing unit of such a semiconductor integrated circuit.
2. Description of the Prior Art
FIG. 1
shows an example of a system LSI formed on a semiconductor chip
10
. The LSI has a central processing unit (CPU)
12
, hardware modules
14
(
14
-
1
to
14
-n), and a memory
16
for storing instructions and data. The CPU
12
executes processes and issues instructions to the modules
14
while monitoring the operating states of the modules
14
. The CPU
12
monitors each module
14
to determine whether the module is processing an instruction, or has completed the processing of an instruction and is waiting for the next instruction, or is sleeping to temporarily stop its operation.
Two techniques for reducing the power consumption of the system LSI shown in
FIG. 1
will be explained. A first technique stops the supply of a clock signal CLK by the CPU
12
to the modules
14
to put the modules into a sleep state while the modules
14
are not operating. A second technique makes the modules
14
automatically put themselves into a sleep state after processing instructions. These techniques make the modules
14
sleep if the modules are not operating, to reduce the power consumption of the chip
10
as a whole. The power consumption of the system LSI, however, is mostly attributed to the CPU
12
. It is important, therefore, to reduce the power consumption of not only the modules
14
but also the CPU
12
.
Reducing the power consumption of the CPU
12
will be realized by putting the CPU
12
into a sleep state if it does not interfere with the operation of the CPU
12
. The CPU
12
can sleep during a period in which the modules
14
are processing instructions and the CPU
12
must wait for the completion of the processes of the modules
14
to start the next substantial process. More precisely, the CPU
12
is idle and can sleep if the modules
14
are executing a first process and if the next substantial process of the CPU
12
is dependent on a result of the first process.
To put the CPU
12
into a sleep state, there is a hardware control technique. This technique is unable to estimate the next operation of the CPU
12
, and therefore, deteriorates the performance of the chip
10
and is inefficient in reducing power consumption. Due to no estimation of CPU operation, the hardware control technique frequently wakes up the CPU
12
just after putting it into a sleep state, or keeps the CPU
12
awaken even when the CPU
12
can sleep. Strictly controlling the timing of putting the CPU
12
into a sleep state needs large hardware that consumes large power. There is a software control technique for putting the CPU
12
into a sleep state. This technique estimates a sleep period of the CPU
12
in advance and issues an instruction to inform the CPU
12
of the sleep period. In response to the instruction, the CPU
12
puts itself into a sleep state. After the completion of the sleep period, the CPU
12
wakes up. If the estimated sleep period is longer than an actual idle period of the CPU
12
, the CPU
12
must uselessly sleep to deteriorate the performance of the chip. On the other hand, if the estimated sleep period is too short, the clock signal CLK will be supplied to the CPU
12
that is still allowed to sleep, thereby wasting power.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit and a power management method for the circuit, capable of properly putting a CPU into a sleep state to reduce power consumption.
In order to accomplish the object, the present invention provides a semiconductor integrated circuit of FIG.
2
. This has a CPU
12
for executing various processes, at least one hardware module
14
for receiving instructions from the CPU and executing the instructions, and a power management device
18
for controlling the supply of a clock signal to the CPU so as to stop the clock signal to the CPU if the CPU has an idle time to start the next process. The power management device
18
is structured as shown in FIG.
6
. Namely, the power management device has a first storage circuit
24
for storing data related to a combination of the hardware modules specified by a sleep instruction, a second storage circuit
26
for storing data indicating whether or not the hardware modules have completed the execution of instructions, a comparator
22
for determining whether or not data in the first and second storage circuits agree with each other, and a controller (28 plus 30) for stopping the supply of the clock signal to the CPU when the sleep instruction is executed and resuming the supply of the clock signal to the CPU when the comparator determines that data in the first and second storage circuits agree with each other.
The present invention employs a sleep instruction to control the timing of making the CPU
12
sleep so that a programmer may optionally determine the timing of putting the CPU
12
into a sleep state. The present invention keeps the CPU
12
sleeping for a correct period without deteriorating the performance of a system LSI in which the CPU
12
is installed. The present invention needs no estimation of a sleep period because the power management device
18
controls the wake-up timing of the CPU
12
and makes the CPU
12
sleep for a proper period. As a result, the present invention greatly reduces the power consumption of the LSI without deteriorating the performance thereof. The power management device
18
is simple in hardware, and therefore, involves a small area and a small power-consumption overhead.
The present invention replaces a conventional termination routine composed of a plurality of instructions with a single sleep instruction, thereby reducing a necessary memory space for storing. instructions, as well as reducing the number of instructions to execute. While the CPU
12
is sleeping, the instruction memory is not accessed so that the instruction memory can also be put into a sleep state. As a result, the present invention reduces the power consumption of not only the CPU but also the instruction memory.
Other and further objects and features of the present invention will become obvious upon an understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.
REFERENCES:
patent: 4891753 (1990-01-01), Budde et al.
patent: 5083266 (1992-01-01), Watanabe
patent: 5734913 (1998-03-01), Iwamura et al.
patent: 5982643 (1999-11-01), Phlipot
patent: 6115806 (2000-09-01), Yoshida
Kawabe Naoyuki
Usami Kimiyoshi
Chang Eric
Kabushiki Kaisha Toshiba
Lee Thomas
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