Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-09-07
2003-05-13
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S267000, C257S316000
Reexamination Certificate
active
06562673
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating flash memory, and more particularly to the fabrication of a self-aligned split gate memory cell of the flash memory.
2. Description of the Prior Art
Complementary metal-oxide-semiconductor (CMOS) memory can be divided into two main categories: random access memory (RAM) and read-only memory (ROM). ROM's market share has been continuously growing in the past few years, and further growth in the near future is foreseen, especially for flash memory in which a single cell can be electrically programmable and a block, sector or page of cells are electrically erasable at the same time. Due to the flexibility of flash memory against electrically programmable read-only memory (EPROM), electrically programmable but erasable via ultraviolet exposure, the market share of flash memory has been continuously growing in the past few years, and further growth in the near future is foreseen. Electrically erasable and programmable read-only memory (EEPROM), electrically erasable and programmable per single byte, will be manufactured for specific applications only, since they use larger area and are more expensive. In recent years, flash memory has found interesting applications in electrical consumer products such as: digital cameras, digital video cameras, cellular phones, laptop computers, mobile MP3 players, and Personal Digital Assistants (PDA's). Since portability of these electrical consumer products is strongly prioritized by consumers, the products' size must be minimal. As a result, the capacity of the flash memory must be enlarged, and functions have to be maximized while size is reduced. The capacity of flash memory has increased from 4 to 256 MB, and even 1 GB in the near future. With the increase in packing density for flash memory, floating gates and control gates have to be made as small as possible. In conventional processes, masks are usually used to define the gates in flash memory.
FIGS. 1A
to
1
F show the manufacturing processes of a conventional split gate flash memory device.
Referring to
FIG. 1A
, a semiconductor substrate
100
is provided, using an LOCOS Oxidation process to form a field insulating layer (not shown) on the substrate
100
. The field insulating layer isolates each Active Area. Then, an ordinary semiconductor process is used to form an oxide layer as the first gate insulating layer
110
. A conductive layer
115
is formed on the first gate insulating layer
110
. The conductive layer
115
is a doped polycrystalline silicon layer formed by CVD process. Then, a first masking layer
120
is formed on the first conductive layer
115
by depositing a silicon nitride layer.
Referring to
FIG. 1B
, the first masking layer
120
is removed by performing an etching process to define the first opening
125
and to expose the surface of the first conductive layer
115
. Then, an oxide layer
130
is formed on the exposed surface of the first conductive layer
115
by an oxidation process.
Referring to
FIG. 1C
, after removing the first masking layer
120
by isotropic etching using oxide layer
130
as the hard mask, a portion of the first conductive layer
115
and the first gate insulating layer
110
are sequentially removed to expose the surface of the substrate
200
by anisotropic etching. The portions of the first conductive layer
115
and the first gate insulating layer
110
under the oxide layer
130
remain. The remaining first conductive layer
115
forms the floating gate
136
. The remaining first gate insulating layer
110
will be expressed as the remaining first gate oxide layer
110
′. A second gate insulating layer
132
is formed on the surface of the substrate
100
, the oxide layer
130
, the floating gate
136
and the remaining first gate oxide layer
110
′. The second gate insulating layer
132
is the oxide silicon and is formed by oxidation or CVD.
In
FIG. 1D
, a second conductive layer
135
is formed by oxidation. The second gate insulating layer
132
is then covered by the second conductive layer
135
.
In
FIG. 1E
, using photolithography and etching, a first opening
142
and a second opening
144
are formed by removing portions of the second conductive layer
135
and the second gate insulating layer
132
. The remaining second conductive layer
135
is the control gate
170
. The remaining second gate insulating layer
132
will be expressed as the remaining second gate insulating layer
132
′ thereinafter. A layer of photoresist fills up the first opening
142
and the second opening
144
, the photoresist in the first opening
142
is then removed. The source region
146
is formed on the exposed substrate
100
by implanting N-type ions, such as Phosphorus or Arsenic into the substrate
100
, which is exposed in the first opening
142
.
In
FIG. 1F
, an oxide layer (not shown) is formed to cover the surface and the side walls of the control gate
170
, the surface of the oxide layer
130
, and the side walls of the remaining second gate insulating layer
132
′, floating gate
136
, the remaining first gate insulating layer
110
′. Etching is performed to remove portions of the oxide layer and form the side wall spacer
150
on the side walls of the floating gate
136
, the remaining first gate insulating layer
110
′, the control gate
170
and the remaining second gate insulating layer
132
′. A layer of photoresist fills the first opening
142
and the second opening
144
, and the photoresist in the second opening
144
is then removed. The drain region
160
is formed on the exposed substrate
100
by implanting N-type ions, such as Phosphorus or Arsenic into the substrate
100
, which is exposed in the second opening
144
. The manufacture of a cell of flash memory is thus completed.
The conventional processes for fabricating flash memory usually use photo masks to define the split gates. As memory devices have become highly integrated, the line width of flash memory has been reduced to under 0.08 &mgr;m or less. The precision of photo masks and photolithography equipment, such as the stepper, have been limited. The misalignment caused by photo masks is difficult to detect. Misalignment easily causes open circuits or short circuits of flash memory device. The electrical character of flash memory then fails and data access error easily occurs. The manufacture of flash memory includes hundreds of process steps and takes weeks or even months. While misalignment happens during photolithography, it is difficult to detect during manufacture due to the limitations of photolithography equipment. Usually, the electrical characteristic tests of flash memory are performed at the end of the manufacturing processes. When the electrical characteristic tests fail at the final tests, many product wafers have to be scrapped. Yield is compromised.
SUMMARY OF THE INVENTION
Accordingly, the primary object of the present invention is to provide a method of fabricating a split gate memory cell of flash memory by self-aligned processes instead of photo masks.
It is the object of the present invention to provide a method of fabricating self-aligned split gate memory cells to reduce the size of the floating gates and control gates of flash memory.
Another object of the present invention is to provide a method of fabricating split gate memory cells of flash memory by self-aligned processes to prevent short circuit or open circuit caused by misalignment of the photo masks in photolithography.
A method of fabricating a self-aligned split gate flash memory cell first provides a substrate. Defining an active area on the substrate, a first gate insulating layer is formed within the active area. A first conductive layer is formed on the first gate insulating layer. Then, a first buffer layer is formed on the first conductive layer. A first opening is formed by removing a portion of the first buffer layer. Afterwards, first buffer spacers are formed on the side walls of the first
Ladas & Parry
Lee Calvin
Nanya Technology Corporation
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