Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-05-22
2003-05-27
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230030
Reexamination Certificate
active
06570803
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a memory system, and more particularly, to a memory system which is capable of increasing the utilization efficiency of a semiconductor memory device and a method of refreshing the semiconductor memory device.
BACKGROUND OF THE INVENTION
Dynamic random accesses memory (DRAM) devices must periodically perform refresh operations. As the storage capacity of memories increases, the time taken to perform a refresh operation increases. When performing a refresh operation, a semiconductor memory device cannot perform other operations. Here, the increase in the time taken for a semiconductor memory device to perform a refresh operation means that a refresh operation accounts for a larger percentage of all operations to be performed by the semiconductor memory device. In other words, a refresh operation makes up a larger percentage of the entire operational time of a DRAM, and thus the utilization efficiency of a memory decreases.
For example, in the case of a 256 Mbit synchronous dynamic random access memory (SDRAM) operating at a frequency of 100 MHz with a refresh time tRFC of 70 ns and a refresh interval of 32 ms and having a page size of 1 Kbyte, the percentage of time necessary for a refresh operation with respect to the total operational time of the SDRAM can be obtained from Equation (1) which assumes a ratio of 8 bits per byte. Here, the refresh time tRFC represents the minimum time taken to activate a wordline and precharge the wordline during a refresh operation.
256
Mbit
1
KByte
×
70
ns
32
ms
=
7.168
%
(
1
)
For a 4 Gbit SDRAM operating at a frequency of 100 MHz with a refresh time tRFC of 70 ns and a refresh interval of 32 ms and having a page size of 4 Kbyte, the percentage of time necessary for a refresh operation with respect to the total operational time of the SDRAM can be obtained from Equation (2).
4
Gbit
4
Kbyte
×
70
ns
32
ms
×
100
=
28.672
%
(
2
)
Referring to Equations (1) and (2), as the memory capacity of a semiconductor memory device increases, the time taken to perform a refresh operation increases.
For currently-used SDRAMs, in order to perform a refresh operation, all banks must be precharged. Thus, in order to re-access a bank which has already been accessed prior to the refresh operation, after the refresh operation, a delay time of as much as tRFC+tRAC is required. Here, tRAC represents the time taken to access memory cells in a wordline after a row active command comes into effect on the wordline.
A solution to the problem of increased time taken to perform a refresh operation can be to provide an SDRAM that is adapted to perform a refresh operation on one bank while performing an operation other than a refresh operation on another bank. However, in order to selectively refresh a particular bank, the address of the particular bank to be refreshed must be applied with a refresh command. In other words, an address field, which indicates the address of the particular bank to be refreshed, must be defined in a refresh operation, and thus the bit efficiency of the refresh operation decreases.
SUMMARY OF THE INVENTION
The present invention, in part according to an embodiment, provides a memory system which is capable of increasing the utilization efficiency of a semiconductor memory device by enabling the semiconductor memory device to selectively refresh fewer, e.g., one of the, banks without having to supply the address of the to-be-refreshed bank in addition to the refresh command. As such, it is possible to substantially simultaneously access banks not currently undergoing the refresh operation, i.e., while performing the refresh operation on the selected bank.
The present invention, also in part according to an embodiment, provides a method of refreshing the semiconductor memory device in the memory system.
The invention, also in part according to an embodiment, provides a memory system comprising: a plurality of semiconductor memory devices, each of which comprises a plurality of banks, each semiconductor memory device being operable to generate the address of a bank to be refreshed next and the address of a wordline to be refreshed as a second refreshed bank address and a refreshed row address, respectively, and to refresh a wordline of a bank corresponding to the second refreshed bank address and the refreshed row address; and a memory controller which generates and outputs a refresh command to the plurality of semiconductor memory devices and generates a first refreshed bank address, which is the same as the second refreshed bank address, in response to the refresh command.
The invention, also in part according to an embodiment, provides a method of refreshing a semiconductor memory device in a memory system comprising a plurality of semiconductor memory devices and a memory controller for controlling the semiconductor memory devices, each semiconductor memory device including a plurality of banks, the method comprising: (a) generating, via the memory controller, the address of a bank to be refreshed as a first refreshed bank address and substantially simultaneously generating, via the semiconductor memory devices, the address of the bank to be refreshed as a second refreshed bank address; and (b) refreshing a bank corresponding to the second refreshed bank address.
The invention, also in part according to an embodiment, provides a method of controlling a memory device to substantially simultaneously undergo a refresh operation and another, non-refresh, operation, the memory device being organized into a plurality of banks, the refresh operation progressing on a bank-by-bank basis, the method comprising: providing a refresh command to the memory device without also providing to the memory device an indication of a corresponding bank address therein initially targeted for refreshing, the refresh command initiating the refresh operation; and providing at least one non-refresh command to the memory device that targets at least one bank in the memory device other than the bank next targeted for refreshing.
The invention, also in part according to an embodiment, provides a memory system comprising: a memory device organized into a plurality of banks; and a memory controller to control the memory device; wherein the memory controller is operable to provide a refresh command to the memory device without also providing to the memory device an indication of a corresponding bank address therein initially targeted for refreshing, the refresh command initiating the refresh operation, the refresh operation progressing on a bank-by-bank basis; and wherein the memory controller is operable to provide at least one non-refresh command to the memory device that targets at least one bank in the memory device other than the bank next targeted for refreshing such that the memory device is controlled to substantially simultaneously undergo a refresh operation and the non-refresh operation.
Additional features and advantages of the invention will be more fully apparent from the following detailed description of the preferred embodiments, the appended claims and the accompanying drawings.
REFERENCES:
patent: 5999472 (1999-12-01), Sakurai
patent: 6141290 (2000-10-01), Cowles et al.
patent: 6233192 (2001-05-01), Tanaka
Lebentritt Michael S.
Phung Anh
Samsung Electronics Co,. Ltd.
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