Trench fill with HDP-CVD process including coupled high...

Details Trench fill with HDP-CVD process including coupled high... Trench fill with HDP-CVD process including coupled high...

2000-05-25

2003-05-06

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S787000, C438S788000, C427S578000, C427S579000, C427S569000

Reexamination Certificate

active

06559026

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the fabrication of integrated circuits. More particularly, the present invention is directed toward a method and apparatus for achieving void-free trench fill on substrates having high aspect ratio trenches.
Semiconductor device geometries continue to decrease in size, providing more devices per unit area on a fabricated wafer. These devices are initially isolated from each other as they are built into the wafer, and they are subsequently interconnected to create the specific circuit configurations desired. Currently, some devices are fabricated with feature dimensions as small as 0.08 &mgr;m. For example, spacing between devices such as conductive lines or traces on a patterned wafer may be separated by 0.08 &mgr;m leaving recesses or gaps of a comparable size. A nonconductive layer of dielectric material, such as silicon dioxide, is typically deposited over the features to fill the aforementioned gap and insulate the features from other features of the integrated circuit in adjacent layers or from adjacent features in the same layer.
Shallow trench isolation (“STI”) is a technique for isolating devices having feature dimensions of under about 1 &mgr;m.
FIG. 1
shows an example of an STI trench substrate
10
, such as a semiconductor wafer, having two islands
12
covered by a trench mask
13
. A trench
14
is disposed between the two islands
12
which define the sidewalls
16
of the trench
14
. The mask
13
is typically a patterned trench mask layer made of a relatively hard material such as silicon nitride (SiN) used in forming the trench. A thermal oxide layer (not shown) is grown on the surfaces of the trench
14
. The silicon nitride mask
13
prevents oxidation of the silicon substrate
10
where active devices are to be formed, and is also referred to as the oxidation mask. The trench
14
is filled by depositing an insulating or dielectric material
18
such as silicon dioxide over the entire trench mask
13
. The silicon dioxide overfills the trench
14
to create an irregular top surface topography. The excess material along with the silicon nitride mask
13
is typically removed to planarize the trench
14
so that the trench-fill material
18
is flush with the islands
12
.
One gap-fill issue encountered when the feature dimensions of the integrated circuits decrease is that it becomes difficult to fill the trenches, as in the case of STI structures. This problem is referred to as the gap-fill problem and is described below in conjunction with
FIGS. 1 and 2
. In the vertical cross-sectional view of
FIG. 1
, the sidewalls
16
of the trench are formed by one edge of each of the two adjacent islands
12
. During deposition, dielectric gap-flu material
18
accumulates on the surfaces
20
of the islands
12
as well as on the substrate surface, and forms overhangs
22
located at the corners
24
of the islands
12
. As deposition of the gap-fill material
18
continues, the overhangs
22
typically grow together faster than the trench
14
is filled until a dielectric layer
26
is formed, creating an interior void
28
, shown more clearly in FIG.
2
. In this fashion, the dielectric layer
26
prevents deposition into the interior void
28
. The interior void
28
can be problematic to device fabrication, operation, and reliability.
Many different techniques have been implemented to improve the gap-filling characterstics of dielectric layers, including deposition etch-back (dep-etch) techniques. One such dep-etch technique involves physical sputtering of the dielectric layer by ion bombardment to prevent the formation of voids during a deposition process. The effects of the physical sputtering dep-etch technique is shown in FIG.
3
. As shown in
FIG. 3
, ions
30
incident on the dielectric material transfer energy thereto by collision, allowing atoms
32
to overcome local binding forces and eject therefrom. During the dep-etch technique, dielectric material fills the trench
14
forming a surface
34
. The surface
34
lies in a plane that extends obliquely to the sidewalls
16
, commonly referred to as a facet. This dep-etch technique may be applied sequentially so that the dielectric layer
26
is deposited and then subsequently etched followed by deposition of additional dielectric material. Alternatively, the deposition process and the etch process may occur concurrently. Whether the deposition and etching are sequential or concurrent, the first order effects on the profile of the surface of the dielectric layer
26
profile are the same.
Typically, a plasma-chemical vapor deposition (CVD) process is employed to deposit a dielectric layer using the dep-etch technique. A plasma is generated to produce chemical reactive plasma species (atoms, radicals, and ions) that are absorbed on the surface of the substrate. For example, a plasma-enhanced chemical vapor deposition (PECVD) process, including a high-density plasma-chemical vapor deposition (HDP-CVD) process (e.g., a plasma formed by applying RF power to an inductive coil or by electron cyclotron resonance chemical vapor deposition (ECR-CVD) process), may be employed. The plasma CVD processes typically allow deposition of high quality films at lower temperature and with faster deposition rates than are typically possible employing purely thermally activated CVD processes.
Referring to
FIGS. 3 and 4
, after an extended dep-etch technique, the portion of the dielectric layer
26
positioned adjacent to the corners
24
, regardless of the spacing between the conductive features
12
, has a surface
34
that forms an oblique angle with respect to the plane in which the substrate
10
lies. Thereafter, planarization may be accomplished by an extended planarization etch technique where physical sputtering is balanced with the deposition so that very narrow features become completely planarized. Alternatively, a separate planarization process may be employed that is capable of smoothing or eliminating the remaining steps of the large features.
Another gap-fill issue arises when the gap dimensions become increasingly narrow and deep so that the void
28
of
FIG. 2
that can form will be deep. Such a gap is characterized by a high aspect ratio, which is defined as the depth of the gap divided by its width, of typically greater than about 3:1. It is difficult to achieve gap fill for deep voids without clipping or sputtering the silicon nitride mask
13
. This clipping problem is described in connection with FIG.
5
. To achieve void-free gap fill, conventional approaches decrease the deposition rate relative to the sputter rate to keep the gap open during the dep-etch process. To continue improving gap fill, lower deposition-to-sputter or deposition-to-etch (dep-etch) ratios become necessary. The lower dep-etch ratio causes the oblique facet
34
to move further apart and closer to the silicon nitride mask
13
. If the dep-etch ratio is sufficiently low, the facet
34
will reach the silicon nitride mask
13
and the comers
24
of the mask
13
will be sputtered or clipped, as illustrated in FIG.
5
. The clipping raises integration concerns during planarization and can lead to gate wrap around and device performance degradation.
Providing void-free gap fill is also important in processes such as the formation of inter-metal dielectric (IMD) layers, and pre-metal dielectric (PMD) layers. In an IMD process, for example, an insulating layer of typically an undoped SiO
2
or fluorine-doped oxide is formed between metal interconnect layers. Although clipping of the metal interconnect layers generally does not occur, similar problems of forming a void-free gap-fill layer with superior gap-filling characteristics arise, particularly for high aspect ratio gaps.
What is needed is a method and an apparatus for depositing a gap-fill layer on a substrate with superior gap filling characteristics and little or no clipping of trench masks or other circuit elements.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for depositing

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