Semiconductor memory device having a fixed CAS latency...

Details Semiconductor memory device having a fixed CAS latency... Semiconductor memory device having a fixed CAS latency...

2000-09-05

2003-05-13

Gossage, Glenn (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S167000, C711S169000, C710S035000, C365S233100, C365S238500

Reexamination Certificate

active

06564287

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to a semiconductor memory device comprising a fixed latency operation mode and/or a fixed burst operation mode.
2. Discussion of Related Art
A conventional semiconductor memory device performing latency and burst operation is designed to perform each of variable operation modes of latency
1
,
2
,
3
, and variable operation modes of burst length
1
,
2
,
4
and
8
.
Here, a latency operation refers to a CAS (column address strobe) latency operation, which is a time delay between the time that effective data is output and the time a read command or signal is applied. CAS latency is given as n clock cycles (where n is an integer). For example, if latency is set at 3, data will be output from a semiconductor device
3
clock cycles after a read command or signal is applied to the semiconductor memory device.
The latency operation of a synchronous dynamic random access memory (SDRAM) is different from that of a double data rate synchronous dynamic random access memory (DDR SDRAM). That is, in case of a SDRAM, if latency is set at n, data is output after being delayed for (n−1)tck(clock cycle)+tsac(a delay time from a clock signal generation to the time when effective data is output) after a read command or signal is input. In case of a DDR SDRAM, data is output after being delayed for ntck(clock cycle)+tsac(a delay time from a clock signal generation to the time when effective data is output) after a read command or signal is input.
A burst operation refers to a situation when a column address is input after a row address is input, and data as to continuous column addresses thereafter is output at high speed in synchronization with a clock signal. For example, if burst length is set at 4, a semiconductor memory device outputs 8 data in synchronization with the clock signal if a column address is input from an external source. Typically, if a column address is input once from the external source, the next 7 column addresses are generated internally by a column address generation circuit.
A conventional semiconductor memory device is usually designed to operate at various latency levels and burst lengths. But, in general, if a semiconductor memory device is used in one system, it operates only in one mode. A semiconductor memory device in a conventional computer typically sets CAS latency at 2 and burst length at 4. Therefore, in most cases, there is no need for designing a semiconductor memory device to perform latency at different levels and burst operations at different lengths.
In order to perform various latency and burst operations like the prior semiconductor memory device, a circuit configuration has to be added internally, and also, when testing the device, the test should be performed in all possible cases of operable latency levels and burst lengths. Consequently, the cost of the device is increased and the test time is increased.
Before describing embodiments of semiconductor memory devices of the present invention, a conventional semiconductor memory device will be described.
FIG. 1
is a block diagram showing a configuration of an embodiment of a conventional semiconductor memory device, comprising a memory cell array
10
, an address buffer
12
, a row address decoder
14
, column selection switches
16
-
1
,
16
-
2
, . . . and
16
-m, a write data amplifier
18
, a sense amplifier
20
, a column address decoder
22
, a mode setting register
24
, a burst address generation circuit
26
, a pipeline control signal generation circuit
28
, a pipeline circuit
30
, a latency enable control signal circuit
32
, and a data output driver
34
.
A configuration of each block shown in
FIG. 1
will now be described in detail. The memory cell array
10
comprises a plurality of memory cells MC connected between n word lines WL
1
, WL
2
, . . . , and WLn and m bit line pairs BL
1
and BL
1
B, BL
2
and BL
2
B, . . . ,and BLm and BLmB respectively. The address buffer
12
buffers and outputs an address Ai applied from an external source. The row address decoder
14
generates n word line selection signals WL
1
, WL
2
, . . . , and WLn by decoding buffered addresses output from the address buffer
12
. The column selection switches
16
-
1
,
16
-
2
, . . . ,and
16
-m operate between bit line pairs BL
1
and BL
1
B, BL
2
and BL
2
B, . . . ,and BLm and BLmB and a data input/output line pair IO and IOB by being turned on in response to each of column selection signals Y
1
, Y
2
, . . . and Ym. The write data amplifier
18
amplifies and transmits data DI input from the external source to the data input/output line pair IO and IOB.
The sense amplifier
20
amplifies data transmitted from the data input/output line pair IO and IOB. The column address decoder
22
generates the column selection signals Y
1
, Y
2
, . . . , and Ym by decoding a burst address PCAj. The mode setting register
24
generates burst length control signals BL
1
,
2
,
4
and
8
and latency control signals CL
1
,
2
and
3
by receiving address Ai in response to a mode setting control signal PMRS. For setting latency level and burst length, the inputted address Ai is inputted through address input pins (not shown). The burst address generation circuit
26
receives a column address in response to a read signal PC and a clock signal CLK, and generates burst addresses starting from the column address in response to the clock signal CLK, and generates burst addresses in lengths corresponding to the burst length control signals BL
1
,
2
,
4
and
8
, and generates a burst length detection signal COSI when the generation of burst addresses is completed. The pipeline control signal generation circuit
28
is enabled in response to the read signal PC and generates pipeline control signals p
1
, p
2
and p
3
by delaying the clock signal CLK in response to the latency control signals CL
1
,
2
and
3
. The pipeline circuit
30
delays and outputs a signal from the sense amplifier
20
in response to the pipeline control signals p
1
, p
2
and p
3
.
The latency enable control circuit
32
generates a latency enable control signal in response to the read signal PC and the burst length detection signal COSI, and delays the latency enable control signal for 1 cycle and 2 cycles in response to the clock signal CLK, and outputs a latency signal, a 1 cycle-delayed latency control signal, or a 2 cycle-delayed latency control signal as a latency enable control signal LA. The data output driver
34
outputs data DO by being enabled in response to the latency enable control signal. The block diagram of an embodiment shown in
FIG. 1
is a configuration inputting/outputting 1 bit data, and the number of bits of input/output data can be extended.
FIG. 2
is a block diagram of an embodiment of a burst address generation circuit shown in
FIG. 1
, which comprises a burst address counter
40
, a burst length counter
42
, a burst length detector
44
and a counter reset circuit
46
. Details of the operation of each block shown in
FIG. 2
will now be described.
The burst address counter
40
receives a column address CAi in response to the read signal PC and outputs a burst address PCAj. The burst address counter
40
further generates addresses, counting up from the input column address CAi in response to the clock signal CLK and outputs the addresses as the burst address PCAj. The burst length counter
42
is operated in response to the read signal PC and generates a signal CNT, counting in response to the clock signal CLK. The burst length detector
44
generates a burst length detection signal COSI if the burst length control signal BL
1
,
2
,
4
and
8
coincides with the signal CNT by comparison. The counter reset circuit
46
is enabled in response to the read signal PC, and generates a reset signal PCAR. The reset signal PCAR is enabled in response to the read command or signal PC and disabled when the burst length detection signal COSI is generated. Then, the genera

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