Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-02-22
2003-09-09
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S554000, C438S003000
Reexamination Certificate
active
06617209
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods for making semiconductor devices, in particular, semiconductor devices that include high-k gate dielectric layers.
BACKGROUND OF THE INVENTION
MOS field-effect transistors with very thin gate dielectrics made from silicon dioxide may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high-k dielectric materials, in place of silicon dioxide, can reduce gate leakage. Such a dielectric may not, however, be compatible with polysilicon—the preferred material for making the device's gate electrode. Placing a thin layer of titanium nitride, which is compatible with many high-k gate dielectrics, between a high-k gate dielectric and a polysilicon-based gate electrode may enable such a dielectric to be used with such a gate electrode. Unfortunately, the presence of such a layer may increase the transistor's threshold voltage, which is undesirable.
Accordingly, there is a need for an improved process for making a semiconductor device that includes a high-k gate dielectric. There is a need for such a process in which a polysilicon-based gate electrode is formed on such a gate dielectric to create a functional device—without causing undesirable work function shifts. The method of the present invention provides such a process.
REFERENCES:
patent: 5625217 (1997-04-01), Chau et al.
patent: 5753560 (1998-05-01), Hong et al.
patent: 5783478 (1998-07-01), Chau et al.
patent: 5891798 (1999-04-01), Doyle et al.
patent: 6063698 (2000-05-01), Tseng et al.
patent: 6087261 (2000-07-01), Nishikawa et al.
patent: 6306742 (2001-10-01), Doyle et al.
patent: 6391802 (2002-05-01), Delpech et al.
patent: 6475874 (2002-11-01), Xiang et al.
Doug Barlage et al., “High-Frequency Response of 100nm Integrated CMOS Transistors with High-K Gate Dielectrics”, 2001 IEEE, 4 pages.
Robert Chau et al., A 50nm Depleted-Substrate CMOS Transistor (DST), 2001 IEEE, 4 pages.
Arghavani Reza
Chau Robert
Doczy Mark
Lee Calvin
Seeley Mark V.
Smith Matthew
LandOfFree
Method for making a semiconductor device having a high-k... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for making a semiconductor device having a high-k..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making a semiconductor device having a high-k... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3083943