Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-19
2003-07-15
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06593182
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method for forming a gate oxide layer, and more particularly to a method for forming a multiple gate oxide layer with the oxygen plasma doping.
2. Description of the Prior Art
As semiconductor devices, such as Metal-Oxide-Semiconductor (MOS) devices, become highly integrated, the area occupied of the chip has to be maintained or more less, so as to reduce the unit cost of the circuit. For corresponding with the development of the high technology industry in the future, there is only one method to achieve this objective, that is, the area occupied by the devices shrinks, as well as the design rule. With advances in the semiconductor technology, the dimensions of the integrated circuit (IC) devices have been shrunk to the deep sub-micron range. As the semiconductor device continuously shrinks to deep sub-micron region, some problems are incurred due to the process of scaling down.
Integrated circuits (IC) are generally constructed from a combination of different devices and isolating structures. The devices are separated from each other through the isolating structures. The most commonly employed isolating structures include shallow trench isolation (STI). For example, the shallow trench isolation separates an input/output (I/O) device area from a core device area. After the formation of an isolation structure, a gate oxide layer is normally formed over the substrate surface. This gate oxide layer serves to facilitate the subsequent formation of a gate or connecting lines. Since a larger voltage is required for controlling the devices in an input/output area compared to a core device area, the input/output area must have a thicker gate oxide layer. Therefore, a thicker gate oxide layer must be formed in the input/output area to protect the devices against any adverse effects caused by a high operating voltage.
In the industry of integrated circuit (IC), it is necessary that the thickness of the dual gate oxide layer or the multiple gate oxide layer is integrated into the simple integrated circuit (IC). The microcontroller units (MCUs) and the digital signal processor (DSPs) use several skill in the simple integrated circuit (IC), such as high speed logic, static random access memory (SRAM), dynamic random access memory (DRAM), nonvolatile memory (NVM). Hence, the process for forming multiple gate dielectric layer in many devices is necessary.
FIGS. 1A through 1D
are cross-sectional views showing the progression of manufacturing steps in the formation of the metal-oxide-semiconductor with a dual gate oxide layer according a conventional method. First of all, a substrate
100
is provided, and a shallow trench isolation
110
is formed in the substrate
100
. Then, a first gate oxide layer
120
having an uniform thickness is formed on the substrate
100
by way of thermal oxidation. Thereafter, a photoresister layer
130
is formed over a partial of the first gate oxide layer
120
. Afterward, removing the portion of the first gate oxide layer
120
without the photoresist layer
130
thereon. Subsequently, removing the photoresist layer
130
, and then proceeding the thermal oxidation process again to form a thin gate oxide layer that is the second gate oxide layer
140
on the substrate
110
and a thick gate oxide layer
150
that is the third gate oxide layer on the first gate oxide layer
120
. Finally, a first gate
160
is formed on the second gate oxide layer
140
and a second gate
170
is formed on the third gate oxide layer
150
, wherein the first gate
160
is a core cell, and the second gate
170
is a I/O buffer region.
According to the conventional process for forming the dual gate oxide layer, as above discussed, there are issues in the conventional process, as follows: firstly, the gate oxide layer of the conventional is formed by way of the furnace process, it has to cost the process time about 6 to 8 hours to complete one batch, so that the throughput can not be increased; secondly, one thickness has to use one photoresist layer, hence, the various thickness of the gate oxide layer that are formed by repeatedly perform the lithography process and oxidation process have consume, hence, the lithography process and oxidation process must be repeatedly performed to form the various thickness of the gate oxide layer, so that the process cost is expensive, and the quality and reliability can not also be increased. Moreover, another method for forming gate oxide layer is performed by ion implantation. If the implanting region is over deep, it will affect the device to cause the channel effect.
In accordance with the above description, a new and improved method for forming the gate dielectric layer is therefore necessary, so as to raise the yield and quality of the follow-up process.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for fabricating the gate dielectric layer that substantially overcomes drawbacks of above mentioned problems arised from the conventional methods.
Accordingly, it is a main object of the present invention to provide a method for fabricating the gate dielectric layer. This invention can use the plasma doping and the thermal oxidation only in one time to substitute for repeatedly proceeding conventional thermal oxidation, so as to reduce times of the lithography process and simplify complex process. This invention can also avoid causing issues of thermal oxidation in many times. Hence, the present invention is appropriate for deep sub-micron technology to provide the semiconductor devices.
Another object of the present invention is to provide a method for forming the gate dielectric layer. The present invention can form an ultra shallow ion-implanting region on the substrate by way of the pulse plasma doping, so as to increase the thickness of gate dielectric layer in follow-up process. Furthermore, this invention can also use various dosage and undoping region with the thermal process only in one time to form the gate dielectric layer having various thickness. Accordingly, this invention can provide a semiconductor device whose performance is better than the conventional one, so as to increase yield and quality of the process and, hence, decrease cost. Therefore, the present invention can correspond to economic effect.
Still another object of the present invention is to provide a method for forming a gate oxide layer with various thicknesses. The present invention can obtain a shallow dosage profile by way of the pulse plasma doping, that is the pulse plasma doping can drive the oxygen to close to the surface of the substrate, so as to avoide the channel of the devices. Furthermore, this method can also reduce the destructiveness of the substrate so that the damage is easy to be repaired during thermal oxidation process, so as to acquire an interface between silicon and silicon oxide in the integrity.
In accordance with the present invention, a new method for forming semiconductor devices is disclosed. First of all, a semiconductor substrate is provided, and then a photoresist layer is formed and defined on the semiconductor substrate. The pulse plasma doping is then performed by the photoresist layer as a mask to form a doping region and an undoping region on the semiconductor substrate. After removing the photoresist layer, performing a thermal oxidation process to form a thick gate oxide layer in the doping region and a thin gate oxide layer in the undoping region. Subsequently, two gates are respectively formed on the thick gate oxide layer and the thin gate oxide layer by means of the conventional process.
REFERENCES:
patent: 5930658 (1999-07-01), Ibok
patent: 6027997 (2000-02-01), Mogami
patent: 6146948 (2000-11-01), Wu et al.
patent: 6335262 (2001-01-01), Crowder et al.
patent: 6319759 (2001-11-01), Furukawa et al.
patent: 6337240 (2002-01-01), Chu
Hoang Quoc
Macronix International Co. Ltd.
Nelms David
Powell Goldstein Frazer & Murphy LLP
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