Method of forming wiring using a dual damascene process

Details Method of forming wiring using a dual damascene process Method of forming wiring using a dual damascene process

2002-07-09

2003-09-09

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S637000, C438S639000, C438S687000, C438S696000, C438S700000

Reexamination Certificate

active

06617232

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming electric wiring in a semiconductor device. More particularly, the present invention relates to a method of forming electric wiring using a dual damascene process in which contacts and conductive lines may be formed simultaneously.
2. Description of the Related Art
Great strides are being made in semiconductor technology as the use of information media, such as computers, continues to increase. To be functionally efficient, semiconductor devices should be operated at a high speed and have a large storage capacity. Accordingly, semiconductor manufacturing technologies are continually being developed to improve the integration degree, reliability and response time of semiconductor devices. One semiconductor technology in particular, a process for forming electric wiring in a semiconductor device, is subject to strict requirements.
Aluminum, which has a low contact resistance that facilitates the electric wiring process, has conventionally been used to form electric wiring in semiconductor devices. If used in highly integrated semiconductor devices, however, aluminum wiring structures may cause various problems, such as a junction spike failure and electromigration. Additionally, a material having a lower resistance than that of aluminum is preferable in order to improve the response speed of the semiconductor device.
Consequently, copper, having a lower resistance and superior electromigration characteristics, is often used together with a low dielectric insulation layer in order to form electric wiring. Copper is rapidly dispersed in silicon and various metal layers, however, so copper has not been adapted for a conventional photolithography process. For this reason, a damascene process is used for forming electric wiring with copper. When forming electric wiring using the damascene process, a dual damascene process wherein conductive lines and contacts may be formed simultaneously, is preferably used for economical reasons.
The dual damascene structure has a via hole where a contact connected to a lower conductor is formed and a trench where a conductive line is formed. The dual damascene structure is achieved by performing one of following etching processes. In a first etching process, the trench is formed after forming the via hole (via-first-forming method). In a second etching process, the via hole is formed after forming the trench (trench-first-forming method). In the third etching process, the via hole and the trench are simultaneously formed (buried-trench-forming method).
The above processes are discriminated from each other by the order in which the via hole and trench are formed in the photolithography and etching processes. The process may be properly selected according to the size of the trench and via hole, the misalign degree of the trench and via hole, etc.
Among the above processes, the via-first-forming method is primarily used because it can simplify the dual damascene structure and reduce misalignment of the trench and via hole.
FIGS. 1A
to
1
D illustrate sectional views showing a conventional method of forming an electric wiring using a dual damascene process.
Referring to
FIG. 1A
, a first insulation layer
10
, having a via hole or a trench filled with conductive material, is formed on a semiconductor substrate (not shown). Accordingly, an upper surface of a conductive pattern
10
a
formed by the conductive material filling the via hole or the trench is exposed at a predetermined portion of an upper surface of the first insulation layer
10
.
Then, an etch stop layer
12
is formed on the first insulation layer
10
. A second insulation layer
14
and a third insulation layer
16
are sequentially formed on the etch stop layer
12
. The third insulation layer
16
is formed of a material having a lower dielectric constant than that of the second insulation layer
14
, and generally has a dielectric constant (k) below 3.5.
Via holes for connecting conductors to each other are formed in the second insulation layer
14
by the next process. The second insulation layer
14
insulates the via holes from each other. In addition, trenches for forming upper conductive lines are formed in the third insulation layer
16
. The third insulation layer
16
insulates the upper conductive lines from each other. Accordingly, the third insulation layer
16
includes a low dielectric material for preventing an increase in capacitance between adjacent upper conductive lines. Generally, the third insulation layer
16
includes carbon or a carbon compound, which is a low dielectric material.
Referring to
FIG. 1B
, a via hole
18
is formed by etching predetermined portions of the third and second insulation layers
16
a
and
14
a
, such that a predetermined portion of the etch stop layer
12
positioned on the conductive pattern
10
a
of the first insulation layer
10
may be exposed. Therefore, the conductive pattern
10
a
is positioned below a bottom of the etch stop layer
12
which is exposed at a lower portion of the via hole
18
.
Referring to
FIG. 1C
, a linear trench
20
partially overlapping the via hole
18
is formed by etching a predetermined portion of the third insulation layer
16
b
. The trench
20
includes the via hole
18
and is formed wider than the via hole
18
. At the trench
20
, the upper conductive line is formed by the next process.
In order to etch the third insulation layer
16
b
including carbon or a carbon compound, a plasma etching process is carried out using C
x
F
y
gas together with mixing gas including oxygen gas and nitrogen gas. Etching gas for etching the third insulation layer
16
b
has a low etching selectivity with respect to the etch stop layer
12
a
. For this reason, when etching the third insulation layer
16
b
, the etch stop layer
12
a
exposed at the lower portion of the via hole
18
b
is etched simultaneously.
If the upper portion of the conductive pattern
10
a
positioned below the etch stop layer
12
a
is exposed due to the etching of the etch stop layer
12
a
, high energy plasma collides with the upper surface of the exposed conductive pattern
10
a
. As a result, a lower portion of the conductive pattern
10
a
, where the contact is to be formed, may be damaged.
Referring to
FIG. 1D
, a conductive material
22
is used to fill the via hole and trench
20
after removing the etch stop layer
12
a
remaining in the lower portion of the via hole
18
b
. Then, a polishing process is carried out such that the conductive material
22
remains only in the via hole
18
b
and the trench
20
, thereby forming the electric wiring.
When forming the electric wiring according to the above-mentioned conventional process, the etch stop layer
12
a
formed at the lower portion of the via hole
18
b
may be etched when etching the trench
20
for forming the conductive line, so that the lower conductive pattern
10
a
becomes damaged. For this reason, it is difficult to achieve a contact having a low resistance.
To solve the problems described above, there has been suggested a method for etching a trench after forming an anti-reflection layer consisting of an organic material in a state that a via hole has been formed. However, in accordance with the method described above, a portion of the third insulation layer to be etched is frequently not etched, thereby causing failure of the semiconductor device.
In addition, the prior art discloses a method of forming a trench in which a spin-on-glass layer is formed after forming a via hole. Then, after forming the trench by etching the third insulation layer, the spin-on-glass layer is removed. However, although using the spin-on-glass layer when etching the trench in this method may protect the lower layer, it is difficult to remove the spin-on-glass layer in a subsequent process. In addition, since the etch stop layer indicating an end point of the etch is not provided when the via hole is formed, a lower conductive pattern may be damaged by the plasma.
SUMMARY OF THE

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