Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2001-11-20
2003-07-15
Le, Thong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S196000, C365S210130
Reexamination Certificate
active
06594187
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-353237, filed Nov. 20, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND
The present invention relates to a semiconductor memory and, more particularly, to a charge transfer sense amplifier for amplifying a small signal read out from a memory cell.
[A]
A current DRAM (Dynamic Random Access Memory) in which a memory cell is comprised of one transistor and one capacitor (1T1C cell) is mainstream.
In a DRAM having a memory cell arrays constituted by such memory cells arranged in the form of a matrix, for example, data read operation is executed in the following steps.
First of all, a bit line is precharged to set it at a precharge potential. The precharging of the bit line is then stopped, and the bit line is set in a floating state. Thereafter, a high potential is applied to a word line to turn on the transfer gate (transistor) of the memory cell.
In this case, since data is stored as the amount of charge stored in the capacitor in the memory cell, when the transfer gate of the memory cell is turned on, the amount of charge corresponding to a data value (“0” or “1”) stored in the memory cell is transferred from the memory cell to the bit line, and the charge is shared between the memory cell and the bit line.
At this time, the potential of the bit line varies from the precharge potential by a value corresponding to the amount of charge output from the memory cell. If, therefore, this change of the potential of the bit line is sensed and amplified by the sense amplifier, data can be read out from the memory cell.
A read scheme in which such a bit line and memory cell (capacitor) share charge will be referred to as a “charge-shared sense scheme”.
In actual data read operation, a pair of bit lines are used. For example, data is output to one of the pair of bit lines, and the other is maintained at the precharge potential (or reference potential). The small potential difference between the pair of bit lines is sensed by the sense amplifier and amplified.
A potential change &Dgr;Vb
1
of a bit line due to cell data (the amount of charge) can be expressed by
&Dgr;Vb
1
=
VBLH/
2·(1+
Cb/Cs
)
where Cb is the bit line capacitance (all the capacitance produced in the bit line), Cs is the cell capacitance (the capacitance of the cell capacitor), VBLH is the “H (High)” level of the potential amplitude of the bit line, and VBLH/2 is the precharge potential of the bit line.
In this case, a ratio Cb/Cs of the bit line capacitance Cb, which serves as a parameter for determining the potential change &Dgr;Vb
1
, to the cell capacitance Cs is preferably minimized.
A 1T1C cell has been used from the days when a DRAM had a memory capacity of several kilobits to the present time when a DRAM at the gigabit level is under development. As a cell data read scheme as well, the above charge-shared sense scheme is generally used.
In the most advanced DRAM, a memory cell array or bit line is divided to decrease the length of each bit line so as to decrease the bit line capacitance Cb.
The cell capacitance (the capacitance of the storage node of the cell capacitor) Cs is increased by forming the cell capacitor into a 3D structure called a trench or stacked structure.
More specifically, in the trench structure, attempts have been made to increase the cell capacitance Cs by increasing the depth of a trench and increasing the aspect ratio of the trench. In the stack structure, attempts have been made to increase the cell capacitance Cs by devising the capacitor shape. There have been tendencies to decrease the Cb/Cs ratio in this manner.
This is because a decrease in the power supply voltage VBLH of a memory cell array associated with the problem of power consumption and a reduction in effective cell capacitance (a reduction in signal amount) due to leakage accompanying the prolongation of a refresh period have been compensated by a reduction in the Cb/Cs ratio.
[Problem 1]
As the size of a MOS transistor has recently been decreased extremely, the gate length has also been decreased very much. A threshold voltage Vth of the MOS transistor abruptly decreases due to the short channel effect as the gate length decreases. As the MOS transistor size decreases, variations in gate length in the manufacturing process lead to great variations in the threshold voltage Vth of the MOS transistor.
Note that a sense amplifier is generally laid out within the pitch of columns. For this reason, as the memory cell size greatly decreases, it is very difficult to reduce variations in the gate length of MOS transistors with a decrease in memory cell size.
[Problem 2]
For the above reasons, the sensing sensitivity of sense amplifiers (the minimum potential difference between a pair of bit lines which is required for a sense amplifier to appropriately amplify cell data) has hardly changed so far.
To accurately detect cell data by using a sense amplifier, therefore, a signal amount larger than a predetermined amount must be ensured.
Recently, however, as the memory cell size has decreased, the bit line capacitance Cb (especially, the capacitance produced between a pair of bit lines) has increased in a trench capacitor type memory cell. In a stack capacitor type memory cell (e.g., a COB (Capacitor Over Bitline) cell), the capacitance produced between a bit line and the storage node (especially, the contact area between a cell capacitor and a cell transistor) of a cell capacitor has increased.
Recently, therefore, with a decrease in memory cell size, it is very difficult to decrease the bit line capacitance Cb, and the bit line capacitance Cb is expected to gradually increase in the future.
It is expected that the cell capacitance Cs in, for example, a trench capacitance type memory cell, will gradually decrease with a decrease in memory cell size because the increase in the aspect ratio of a trench has approached to the process limit, and a decrease in the thickness of a capacitor insulating film is very difficult to attain in consideration of leak current and reliability. With the reduction in memory cell size, the power supply voltage (internal power supply voltage VBLH) of a memory cell array portion decreases. For this reason, it is difficult to keep the amount of signal read from a memory cell constant.
As described above, recently, as the memory cell size has decreased, it has been difficult to decrease the Cb/Cs ratio, and the Cb/Cs value has tended to increase. For this reason, the amount of signal read out from a memory cell decreases, and the potential difference between a pair of bit lines becomes less than the sensing sensitivity of the sense amplifier. As a consequence, the sense amplifier cannot sense cell data.
As for the increase in the cell capacitance Cs, a technique using a high dielectric constant film as a capacitor insulating film for a cell capacitor has been studied. It is expected that if this technique is put into practice, this problem will be left unsolved for the time being. It is, however, said that it will become impossible to read out data from a DRAM using 1T1C cells by the charge-share sense scheme in the near future.
As described above, in data read operation based on the charge-shared sense scheme, a bit line and a cell capacitor are electrically connected to each other to share charge. For this reason, with a reduction in memory cell size, as the cell capacitance Cs decreases and the bit line capacitance Cb increases, the amount of charge (signal amount) read out from the memory cell greatly decreases. As a result, the sense amplifier cannot detect cell data.
As precharge schemes for bit lines in data read operation, for example, the VBLH precharge scheme, VBLH/2 precharge scheme, and the like are known. In the VBLH/2 precharge scheme, as the voltage of the memory cell array portion decreases, the operation speed greatly decreases.
The fundamental problem that the amoun
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