Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-16
2003-07-08
Fahmy, Jr., Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S382000, C257S900000
Reexamination Certificate
active
06590265
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to semiconductor integrated circuits (ICs) and methods of fabrication thereof, and more specifically to a semiconductor IC with minimized dimensions for contact openings and methods for the fabrication of thereof.
2. Related Art
The ability to scale the size of semiconductor device geometries downward is key to meeting the demands for integrated circuits having increased functionality and performance while maintaining low fabrication costs. The industry's ability to meet this demand to date has very much been due to improvements in the optical resolution of photolithography equipment and associated processes. However, the full impact of these improvements is often not realized, as process buffering regions are needed to account for registration and other process tolerances. This is particularly true for contact openings.
For example, in the manner of the prior art,
FIG. 1A
depicts a plan view of a first contact opening
40
formed overlying a first conductive trace
30
. Typically, both first trace
30
and first contact opening
40
are formed having a minimum design dimension. Thus, first trace
30
has a width
50
and first contact
40
a width
52
that are essentially equal. However, to ensure that first contact
40
overlies only first trace
30
, contact
40
is positioned within a contact region
34
, an expanded region of trace
30
, that has a dimension
54
, larger than widths
50
and
52
. The size difference between width
54
and width
50
is the amount of process buffering required to form first contact
40
entirely overlying conductive trace
30
. Therefore despite less than perfect alignment of first opening
40
to first trace
30
, as depicted, contact opening
40
is fully within contact region
34
. Where a second conductive trace
32
does not provide any process buffering region, that is no region analogous to expanded region
34
, the less than perfect alignment of a second contact opening
42
to second trace
32
results in second contact opening
42
being positioned having a portion of second contact
42
off second trace
34
, as depicted. As known, such mis-positioning can result in both yield and reliability problems. Thus to avoid these problems, prior art processing provides process buffering regions.
Expanded process buffering regions, such as contact region
34
, are not the only forms of process buffering regions employed in the prior art. Turning now to
FIG. 1B
, a plan view of an MOS transistor
90
is shown. An active area
80
has source and drain (S/D) regions
60
formed therein. S/D regions
60
are respectively electrically contacted through S/D contact openings
62
. A gate electrode
70
is disposed adjacent to and between S/D regions
62
and overlying a channel region (not shown) in active area
80
bordered by S/D regions
60
. Electrical contact to gate electrode
70
is made through a gate contact opening
72
within a process buffering region
74
extending outward from area
80
, as depicted. As known, an extended process buffering region, such as region
74
, is often employed in prior art MOS transistors for providing electrical contact to gate electrode
70
.
Use of an expanded buffering region, such as region
34
of
FIG. 1A
, is problematic as such an expanded region increases gate length. As known, an increased gate length will result in a change in the electrical characteristics of transistor
90
from that of a transistor having the nominal gate length. On the other hand, failure to use any process buffering region, as shown for second contact
42
in
FIG. 1A
, can result in lowered yield and reliability due to electrical shorting of gate
70
to S/D regions
60
. Therefore the-prior art process and MOS transistors formed thereby, require that an extension of gate
70
be employed to form process buffering region
74
and that gate contact opening
72
be disposed within extended region
74
. Hence it can be seen that contacts formed in the manner of the prior art require either expanded process buffering regions or extended process buffering regions. These buffering regions require substrate surface area in excess of that required by the functional structures themselves, for example trace
32
and contact
42
of FIG.
1
A. Thus, processing in the manner of the prior art does not allow for the full realization of the benefits that downward scaling of device structures can provide.
Thus it would be advantageous to have IC structures and devices that realize the full benefit of scaling the size of such structures and devices downward, and the methods of manufacture thereof. It would also be advantageous to have methods for forming such fully realized size scaled devices and structures that do not require additional photomasking processes. In addition it would be advantageous for such methods of manufacture to be broadly applicable, thus providing for the manufacture of both MOS and Bipolar devices as well as any combination of such devices thereof that fully realize such size scaling. Finally, it would be advantageous to manufacture such fully realized size scaled devices in a cost effective manner so that they have yield and reliability at least equal to that of the prior art.
SUMMARY
In accordance with the present invention, methods for forming minimized area contact structures, and the structures and IC's formed thereby, are provided. In some embodiments of the present invention, MOS integrated circuits and circuit elements are formed. In some embodiments of the present invention, bipolar integrated circuits and circuit elements are formed and in some embodiments, both MOS and bipolar circuit elements and circuit elements are formed.
In accordance with the present invention some embodiments employ a non-conductive material to form process buffering regions adjacent conductive traces. In some embodiments the non-conductive material employed is a dielectric material such as silicon oxide, silicon nitride or a combination of silicon oxide and silicon nitride. In some embodiments both silicon oxide and silicon nitride materials are employed. In some embodiments of the present invention the dielectric material is formed as a layer overlying a semiconductor substrate and selectively etched to form process buffering regions or process buffering spacers adjacent sidewalls of the conductive traces formed on the substrate. In some embodiments process buffering spacers are formed using more than one layer of dielectric material.
Embodiments in accordance with the present invention typically employ a dielectric layer disposed over the process buffering regions. In some embodiments, the material of the process buffering regions is selectively etchable with respect to the dielectric layer. In some embodiments the dielectric layer is formed of more than one layer of dielectric material, each layer being selectively etchable with respect to an underlying layer. In some embodiments of the present invention contact holes or vias are formed by etching portions of the dielectric layer left exposed after deposition and patterning of a photomasking layer to define such portions. In embodiments where a conductive trace is a gate electrode, process buffering regions formed in accordance with the present invention allow direct contact to be made to the gate electrode, if desired. Finally, in some embodiments, the process buffering regions formed, prevent exposure of sidewalls of the conductive traces. In this manner, embodiments in accordance with the present invention avoid the need for formation of either expanded or extended process buffering regions, thus enabling minimized area contacts.
REFERENCES:
patent: 5321211 (1994-06-01), Haslam et al.
patent: 5811350 (1998-09-01), Dennison
patent: 5858848 (1999-01-01), Gardner et al.
patent: 6037232 (2000-03-01), Wieczorek et al.
patent: 6093629 (2000-07-01), Chen
Fahmy Jr. Wael
Meetin Ronald J.
National Semiconductor Corporation
Pham Hoai
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