Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-11-19
2003-07-08
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S233100, C365S194000
Reexamination Certificate
active
06590823
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to a dynamic random access memory capable of performing refresh operation independently of input signals received from external sources (which will hereinbelow be referred to as a “complete-hidden-refresh-function-included DRAM”).
2. Description of the Background Art
In a field of portable terminals such as portable telephones, there is widely used an asynchronous general-purpose static random access memory (which will hereinbelow referred to as “SRAM”) for which external clocks need not be supplied. In the SRAM, since refresh operation need not be performed, complex control need not be performed. For example, the SRAM need not perform control access that is made to the memory in refresh operation by awaiting completion of a refresh cycle. In view of the above, the SRAMs are suitable for use with the portable terminals.
Recently, since a portable terminal handles images, the function thereof has been significantly improved, and the portable terminal requires large scale memory functions. However, the SRAM has memory which is about 10 times that of a dynamic random access memory (which hereinbelow will be referred to as a “DRAM”). For a large-scale SRAM, the cost for the memory chip is significantly increased, and consequently, the price of the portable terminal is increased. To cope with the problem, a technical scheme has been conceived in which, instead of the SRAM, a DRAM of which memory cost per unit bit is lower is used with the portable terminal.
However, the DRAM requires complex memory control relative to refresh operation. For portable-terminal manufacturers that hitherto have been engaged in design of systems using SRAMs as memories, it is not easy to use DRAMs as substitutive memories of SRAMs.
Under these circumstances, many semiconductor manufacturers have begun the development of a new semiconductor memory device. The new memory device is formed of a DRAM, but it operates as a SRAM in terms of external functions. The new semiconductor memory device is introduced in “Kazuhiro Sawada, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 23, No.1, February 1998, (pp.12-19)”. Hereinbelow, the new semiconductor memory device is referred to as a “complete-hidden-refresh-function-included DRAM”.
In the complete-hidden-refresh-function-included DRAM, the same memory cells as those used in the DRAM are used. On the other hand, external interfaces, such as control signals and address signals to be input to the complete-hidden-refresh-function-included DRAM, are the same as those to be input to the SRAM. However, different from refresh operation or self-refresh operation of the conventional DRAM, refresh operation of the complete-hidden-refresh-function-included DRAM is not controlled by signals externally supplied. In specific, the refresh operation is controlled by a refresh command signal /REFE that is cyclically output from a refresh circuit provided in the complete-hidden-refresh-function-included DRAM. The refresh circuit includes a ring oscillator as a timer circuit, and outputs refresh command signal /REFE in response to a cycle signal /Refcyc that is cyclically output from the timer circuit.
FIG. 13
is a timing chart representing a case where refresh operation is executed in a conventional complete-hidden-refresh-function-included DRAM.
In
FIG. 13
, a timer circuit in the complete-hidden-refresh-function-included DRAM cyclically activates cycle signal /Refcyc, and also activates refresh command signal /REFE in response to the activation of cycle signal /Refcyc. Thereby, the complete-hidden-refresh-function-included DRAM cyclically executes refresh operation either in an operation state where either read operation or write operation for data is readily executable or in a standby state where the data is retained.
As described above, however, the complete-hidden-refresh-function-included DRAM executes refresh operation independently of input signals externally supplied. This causes a problem in that although attempt is made to perform testing for evaluation of refresh characteristics, the testing cannot be performed for observation and evaluation of refresh characteristics.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device including a complete hidden refresh function that enables testing to be performed for observation and evaluation of refresh characteristics.
A semiconductor memory device of the present invention allows testing to be performed and includes a memory cell array including a plurality of memory cells arranged in a matrix, input-terminal group through which external signals are input, and a complete hidden refresh circuit capable of performing refreshing operation without being externally commanded for data stored in the plurality of memory cells. A function of the complete hidden refresh circuit is invalidated in response to a signal input through the input terminal group.
Preferably, the complete hidden refresh circuit includes a refresh circuit for outputting a refresh command signal for commanding execution of the refresh operation, a control circuit for executing the refresh operation in response to the refresh command signal, in which the function of the refresh circuit is invalidated in response to a signal output from the input terminal group.
In this case, the refresh operation can be forcedly terminated according to an externally input signal, and refresh characteristic evaluation testing can thereby be performed.
In addition, the refresh circuit preferably includes a timer circuit for outputting a cycle signal at a time interval required to refresh the data stored in the plurality of memory cells, a command-signal activating circuit for activating the refresh command signal in response to the cycle signal, a determination circuit for determining as to whether or not the refresh command signal activated needs to be output.
Furthermore, a function of the timer circuit is preferably invalidated in response to a signal input from the input terminal group.
In this case, the refresh operation can be terminated by invalidating the cycle signal that is output from the timer circuit, and the refresh characteristic evaluation testing can therefore be performed.
Still furthermore, a function of the command-signal activating circuit is preferably invalidated in response to a signal input through the input terminal group.
Because of the above arrangement, the command-signal activating circuit is disabled to activate the refresh command signal, and consequently, the refresh operation terminates. Thereby, the refresh characteristic evaluation testing can be performed.
Still furthermore, a function of the determination circuit is preferably invalidated in response to a signal input through the input terminal group.
In this case, the refresh operation can be terminated by invalidating a determination signal that is output from the determination circuit, and the refresh characteristic evaluation testing can thereby be performed.
According to the present invention described above, in the complete-hidden-refresh-function-included DRAM, an external signal is used to terminate the complete-hidden-refresh-function-included DRAM, thereby enabling refresh characteristic evaluation testing to be implemented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5715206 (1998-02-01), Lee et al.
patent: 6327210 (2001-12-01), Kuroda et al.
patent: 6-119780 (1994-04-01), None
Sawada, et al., “A 30-&mgr;A Data-Retention Pseudostatic RAM with Virtually Static RAM Mode,” Feb. 1988, pp. 12-19, IEEE Journal of Solid-State Circuits, vol. 23, No. 1.
Lam David
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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