Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2001-06-13
2003-08-05
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S189050, C365S194000, C365S207000, C365S214000, C365S230060, C365S230080
Reexamination Certificate
active
06603692
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device. In particular, it relates to a semiconductor memory device layout so that the read-out speed of the semiconductor memory device can be high.
2. Description of a Related Art
Efforts for improving integration and capacity of semiconductor memory devices have been continuously made so that many memory cells can be connected to pairs of digit lines. Accordingly, the capacitance on digit lines becomes large, causing the access delay to increase, preventing the high speed operation from being performed. To solve this problem, the inventor of the present invention supposed that pre-charge circuits are deployed at both ends of the digit lines, for example, so that the high speed recovery (pre-charge) after a writing is performed can be performed.
FIG. 1
is a diagram showing the layout of a chip of a semiconductor memory device of a related art, supposed by the inventor. On semiconductor chip
1
input buffers such as word selection signal input buffers
2
, block selection signal input buffers
3
, and column selection signal input buffers
4
are provided; wherein for each input buffer, word signal decoder
5
, which decodes the respective each output signal of it, block signal decoder
6
, and column signal decoder
7
are provided. At the output end of each decoder, word signal driver
8
, block signal driver
9
, and column signal driver
10
, which function as buffers for the output signals of the respective decoders, are provided. These drivers
8
to
10
are deployed along the longer sides of the chip.
In the middle of the chip, memory blocks BL
0
to BL
31
are laid out. A memory cell array of memory cell block
11
, near-end side pre-charge unit
12
, and far-end side pre-charge unit
13
are provided in each memory block BL
0
to BL
31
. In near-end side pre-charge unit
12
, sense amplifiers are provided. The output signals of column selection/pre-charge control NAND gates G
0
to G
15
, which select a column of memory cells in the memory block, are input to each near-end side pre-charge unit
12
.
In this Figure, in order to simplify the description, it is assumed that the number of word selection signals is three, and the number of block selection signals and the number of column selection signals are four bits, respectively. The output of word selection signal input buffers
2
is decoded by word signal decoder
5
, input to word signal drivers
8
, and coupled to eight word lines in each memory block BL
0
to BL
31
through word signal lines
14
.
In the same manner, the output of block selection signal input buffers
3
is decoded by block signal decoder
6
, input to block signal drivers
9
; the output of which being then input to the respective far-end side pre-charge unit
13
for each memory block BL
0
to BL
31
and one of the input terminal of each NAND gate G
0
to G
15
through each block selection signal line
15
.
The output of column selection signal input buffers
4
is decoded by column signal decoder
7
, and then input to the other input terminals of NAND gates G
0
to G
15
through each respective column signal driver
10
.
With such configuration, one of eight word lines is selected for thirty-two memory blocks on a single chip so that a single line of memory cells in all the memory blocks may be selected; and the NAND gates connected to either of the two memory blocks are selected by the sixteen block selection signal lines
15
.
In such a semiconductor memory device as described above, far-end side pre-charge units
13
are deployed at the farthest position from the each of the respective block signal drivers
9
. Accordingly, when the pre-charge operation of the pre-charge circuit is halted for, for example, a read-out operation, transmission of the signal therein takes time causing the halt point in time for the pre-charge operation to be later than the halt point in time of near-end side pre-charge units
12
. Besides this, the word lines for the memory cells on the far-end side pre-charge sides of the memory blocks BL are deployed far from word signal drivers
8
. Accordingly, the point in time at which a word line is selected for, for example, the read-out operation is later than the point in time at which the word line positioned near near-end side pre-charge units
12
is selected. Furthermore, the transmission time for the signal that is read out to the digit line of the memory cell, which is deployed near far-end side pre-charge unit
13
, to reach the corresponding sense amplifier is longer than the transmission time in the case where the memory cell deployed near near-end side pre-charge unit
12
is read out.
In other words, the point in time at which an operation of reading out from the memory cell block deplored near far-end side pre-charge unit
13
where transmitting the read-out signal takes a longer amount of time is later than the start point in time for the memory cell block deployed near near-end side pre-charge unit
12
, making it difficult to provide high-speed operation.
The subject of the present invention is to solve the above-mentioned problem, and its objective is to provide a high access speed semiconductor memory device, which is configured with the point in time at which changing from the pre-charge operation to the wordline selection operation, which is performed on the near-end side of each sense amplifier, being no later than the point in time at which the same is performed on the far-end side of each sense amplifier, in order to improve the speed at which reading out the memory cells deployed far from each sense amplifier is performed.
SUMMARY OF THE PRESENT INVENTION
According to an aspect of the present invention, there is provided a semiconductor memory device, which includes a memory cell deployed in a column direction, a pair of digit lines connected to each memory cell, a word line, which is laid crossing said digit lines and selects each memory cell, a sense amplifier, which is positioned on one side of said digit lines, a near-end side pre-charge circuit, which is deployed near said sense amplifier of said digit lines, and a far-end side pre-charge circuit, which is deployed at the opposite end to said sense amplifier of said digit lines. This semiconductor memory device is characterized by the completion point in time of a pre-charge operation of a far-end side pre-charge circuit during a read-out operation being earlier than that of a near-end side pre-charge circuit.
According to an aspect of the present invention, it is preferred that; during a read-out operation, the selection signal for the word line located near the far-end side pre-charge circuit climb up earlier than the word line located near the near-end side pre-charge circuit.
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Choate Hall & Stewart
Ho Hoai
NEC Electronics Corporation
Pham Ly Duy
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