Method of manufacturing a vertical semiconductor device with gro

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

438656, 438665, 438928, 438977, 438586, H01L 2144

Patent

active

056630964

ABSTRACT:
A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

REFERENCES:
patent: 4859629 (1989-08-01), Reardon et al.
patent: 4879250 (1989-11-01), Chan
patent: 4927784 (1990-05-01), Kazior et al.
patent: 4931412 (1990-06-01), Fischer et al.
patent: 4985740 (1991-01-01), Shenai et al.
patent: 5242862 (1993-09-01), Okabe et al.
patent: 5338961 (1994-08-01), Lidow et al.
Krishna Shenai et al, "A 50-V, 0.7m.OMEGA..cndot.cm.sup.2, Vertical-Power DMOSFET", IEEE Electron Device Letters, vol. 10, No. 3, Mar. 1989, pp. 101-103.
Krishna Shenai, "Optimally Scaled Low-Voltage Vertical Power Mosfet's for High-Frequency Power Conversion", IEEE Transactions on Electron Devices, vol. 37, No. 4, Apr. 1990, pp. 1411-1453.
Shin-ichi Ogawa et al, "HRTEM and Nano-Scale Micro Analysis of the Titanium/Silicon Inter-Facial Reaction Correlated with Electrical Properties", Extended Abstracts of the 22nd 1990 International Conference on Solid State Devices and Materials, 1990, pp. 429-432.
C. Y. Ting et al, "The Use of Titanium-Based Contact Barrier Layres in Silicon Technology", Electronics and Optics, Thin Solid Films 96, 1982, pp. 327-345 (USA).
Krishna Shenai, "A 50-V, 0.7-m.OMEGA..cm.sup.2 Vertical-Power DMOSFET", IEEE Elect. Device Letter, vol. No. 10. No. 3 Mar. 1989.
S. Ogawa et al, "HRTEM and Nano-Scale Micro Analysis of the Titanuim/Silicon Interfacial Reaction Correlated with Electrical Properties", Extended Abstract of the 22nd Conference.., 1990 pp. 429-432.
C.Y. Ting et al, "The Use of Titanium-based Contact Barrier Layers in Silicon Technology", Thin Solid Films, 96(1982) 327-345 Electronics and Optics.
Semiconductor Devices-Physics and Technology, Jan. 1985 S.M. Sze p. 307.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of manufacturing a vertical semiconductor device with gro does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing a vertical semiconductor device with gro, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a vertical semiconductor device with gro will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-307697

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.