SOI DRAM without floating body effect

Details SOI DRAM without floating body effect SOI DRAM without floating body effect

2002-03-11

2003-07-29

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S391000

Reexamination Certificate

active

06599797

ABSTRACT:

The invention relates to a substrate having a monocrystalline-silicon layer, an SiO
2
layer arranged below and a silicon substrate arranged underneath, as well as to a method for its fabrication.
Such a substrate is referred to in the specialist field as an SOI substrate. The use of an SOI substrate instead of a customary silicon substrate for integrated semiconductor components offers a number of advantages. For instance, owing to the small thickness of the monocrystalline-silicon layer, which is customarily between 50 nm and 200 nm, active regions of the semiconductor components may be completely surrounded by insulating structures. To that end, installation trenches produced starting from one surface of the SOI substrate extend as far as the SiO
2
layer. The complete insulation of the active regions avoids leakage currents between semiconductor components that neighbor one another. It is also possible to avoid short channel effects in transistors. A further advantage of using an SOI substrate is that capacitances at pn junctions are very small since no space-charge regions can be formed under the pn junctions, so that the switching speeds of the semiconductor components can be increased greatly and the semiconductor components' power consumption can be lowered greatly. If a DRAM cell arrangement is produced in an SOI substrate, then any bit line capacitance can be reduced greatly for the same reason.
However, complete insulation of the active region also leads to negative effects, which are known as floating body effects. These effects are due to the fact that charge carriers created in the active region cannot be dissipated. This is particularly relevant to charge carriers produced in a channel region of a MOS transistor.
An SOI substrate, in which floating body effects are avoided, is described in Cuong T. Nguyen et al. “Quasi-SOI MOSFETs Using Selective Epitaxy and Polishing”, IEDM (1992), 341. The SiO
2
layer is not continuous, but rather is interrupted by a silicon column. The silicon layer is not continuous either, but rather is embedded in an upper part of the SiO
2
layer. The silicon column connects the silicon substrate to the silicon layer. A MOS transistor is arranged in the silicon layer in such a way that a channel region of the MOS transistor is connected to the silicon column. The channel region of the MOS transistor is hence connected to the silicon substrate through the silicon column, so that charge carriers produced in the channel region can be dissipated and floating body effects are avoided. To produce the SOI substrate, the SiO
2
layer is produced on the silicon substrate and is patterned with the aid of two masked etching processes. During these, on the one hand, a recess, in which the silicon column will be produced at a later time, is produced as far as the silicon substrate. On the other hand, SiO
2
is etched, in the environment of the recess, to a substantially smaller depth than the recess. By selective epitaxy and subsequent chemical-mechanical polishing until a surface of the SiO
2
layer is exposed, the silicon column as well as, in the environment of the recess, the silicon layer is produced.
Y. Nishioka et al. “Giga-bit Scale DRAM Cell with New Simple Ru/(Ba,Sr)TiO
3
/Ru Stacked Capacitors Using X-ray Lithography” IEDM (1995) 903, describes a DRAM cell arrangement in which a memory cell comprises a transistor and a capacitor. The transistor is a planar transistor, and its gate electrode is part of a word line that extends along a surface of a substrate in which the DRAM cell arrangement is arranged. Two transistors of two memory cells respectively share a common source/drain region that is connected to a bit line. The transistor has a further source/drain region, which is connected through a contact to a capacitor. The common source/drain region has a first part and a second part, which are respectively arranged between the word line and a neighboring word line and which adjoin one another. A connecting line drawn through the second part of the common source/drain region, the further source/drain region of the transistor and the further source/drain region of the neighboring transistor, is straight. The bit line is connected to the first part of the common source/drain region. Insulating structures laterally separate from each other source/drain regions of transistors of memory cells that neighbor one another along the word line. The insulating structures furthermore laterally separate from each other the further source/drain regions, which are connected to capacitors of memory cells that neighbor one another along the bit line.
The term “cylinder” denotes a body that is bounded by two parallel planes and a surface that is created by parallel displacement of a straight line along a space curve (cf. e.g. “Meyer's Lexikon”). If the space curve is a circle, then the term “circular cylinder” is used. In particular, a cuboid is also a cylinder. The term “cylinder” will also be used below to denote a body or a shape that deviates slightly from the mathematically rigorous cylinder. The deviation may be due e.g. to irregularities during etching processes, to deposition methods in which recesses are not completely filled in the vicinity of edges, or to the provision of auxiliary structures that are advantageous for a fabrication method and may e.g. narrow a part of the cylinder.
It is an object of the invention to provide a further SOI substrate in which the monocrystalline-silicon layer is connected to the silicon substrate, and which is suitable for an integrated semiconductor component in which floating body effects are avoided. It is also an object to provide a method for fabricating such an SOI substrate.
The object is achieved by an SOI substrate in which a recess is provided that cuts through a silicon layer and an SiO
2
layer arranged below. An upper part of the recess, which part is arranged in the vicinity of the silicon layer, has a cylindrical shape with a horizontal first cross section. A lower part of the recess, which part is arranged in the vicinity of the SiO
2
layer, is bulged relative to the upper part of the recess such that it has a cylindrical shape with a horizontal second cross section that is larger than the first cross section. A cylinder of insulating material has a horizontal cross section that corresponds to the first cross section. A lower part of the cylinder is arranged in the lower part of the recess. The bulge is configured such that it laterally surrounds the lower part of the cylinder. A conductive structure, which adjoins the silicon layer and a silicon substrate, on which the SiO
2
layer is arranged, is arranged in the bulge.
The silicon layer is connected to the silicon substrate through the conductive structure.
The object is furthermore achieved by a method for producing an SOI substrate, in which a recess that cuts through a silicon layer and an SiO
2
layer arranged below is produced in the SOI substrate by anisotropic etching. A lower part of the recess, which part is arranged in the vicinity of the SiO
2
layer, is widened by isotropic etching of SiO
2
selectively with respect to silicon so that it has a bulge relative to an upper part of the recess, which part is arranged in the vicinity of the silicon layer. Subsequently, conductive material is deposited substantially conformally and etched back until a bottom of the recess is exposed, so that a conductive structure, which adjoins the silicon layer and the silicon substrate, is produced in the bulge. Subsequently, insulating material is introduced into the recess so as to produce a cylinder, the lower part of which is arranged in the lower part of the recess and is laterally surrounded by the conductive structure.
The method may be carried out starting with commercially available SOI substrates, in which the conductive structure is subsequently produced. The production of the conductive structure does not require any elaborate process steps, such as selective epitaxy.
Examples of suitable conductive material for the conductive struct

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