Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-02-18
2003-05-20
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06567939
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, a merged data line test circuit for combining a plurality of data lines and testing the merged data lines, and a test method performed with the test circuit.
2. Description of the Related Art
After manufacture of a semiconductor memory device such as a DRAM, a test certifies the memory cells of the device by testing writing, reading, or other operations of the device. With an increase in the memory capacity of a DRAM, the time required for this testing also increases. For example, in a 64 Mbit synchronous DRAM, a simple test procedure in which a data value of “0” or “1” is written to all memory cells and then read from every memory cell, requires about 24 seconds (or 90×10
−9
s×4×64×(1024)
2
) when 90 ns is the period of the clock signal for the synhronous DRAM. When several millions of DRAMs are produced each month, the time required for testing the DRAMs is significant. This test time raises the testing costs and degrades productivity. Thus, methods for reducing the test time are sought.
A parallel bit test method, which can be performed by a merged data line test circuit, tests several memory cells at the same time to reduce the test time. The merged data line test circuit merges a plurality of data lines for comparing data and base on the comparison determines whether a set of memory cells are all good or contain a bad (or defective) memory cell. In synchronous DRAMs, which operate in synchronization with a clock signal, the merged data line test circuit tests data from multiple memory cell data during a single clock cycle. If the testing detects a defect, the circuit needs to ascertain which memory cell is defective for a possible repair operation using redundant memory cells. However, the conventional merged data line test circuit simultaneously tests memory cell data without classification, so that, when a defect is detected, identifying the defective memory cell is difficult.
Therefore, a merged data line test circuit, which can determine the position of a defective cell, is sought.
SUMMARY OF THE INVENTION
In accordance with an aspect of the present invention, a merged data line test circuit classifies and tests a plurality of data lines and can easily determine the position of a defective cell when a test detects a defect.
In one embodiment of the invention, a merged data line test circuit classifies a plurality of data lines into upper and lower data lines and simultaneously or separately tests the upper or lower data lines. The test circuit includes a control signal generator, a first comparison unit, a second comparison unit, and a driver. The control signal generator generates first and second control signals in response to a separated-test signal and a merged-test signal. The separated-test signal is for directing the data lines to be separated into upper and lower data lines and then tested, and the merged-test signal is for directing the combination test. The first comparison unit compares the data lines in the upper data line group in response to the first control signal, and the second comparison unit compares the data lines in the lower data line group in response to the second control signal. The driver outputs merged data signal according to the output signals of the first and second comparison units. Preferably, the separated test alternatively activates the first and second control signals. The signal generator simultaneously activates the first and second control signals in response to the merged test signal.
In accordance with another embodiment of the invention, a testing method includes: (a) activating both first and second control signals in response to a merged-test signal; (b) simultaneously comparing the data lines using first and second comparison units which respectively respond to the first and second control signals; (c) alternately activating the first and then second control signal in response to a separated-test signal; and (d) outputting merged data signals according to the output signals of the first and second comparison units.
In the merged data line test circuit and method according to the present invention, when a defect is detected as the result of simultaneously testing a plurality of data lines, the data lines are separated and re-tested. In this way, the positions of defective cells can be easily determined.
REFERENCES:
patent: 5077689 (1991-12-01), Ahn
patent: 5311473 (1994-05-01), McClure et al.
Mori et al., A 45ns 64 mb DRAM with Merged Match-line Test Architecture, IEEE, p. 110-113, 1991.*
Matsuda et al., A New Array architecture for PArallel Testing in VLSI Memories, IEEE, p. 322-326, 1989.*
Japanese Laid-open Patent Publication No. hei 4-243099 (published Aug. 31, 1992) including Patent Abstract of Japan JP4243099.
Korean Laid-open Patent Publication No. 93-18592 (published Sep. 22, 1993) including Patent Abstract.
Chase Shelly A.
Harness & Dickey & Pierce P.L.C.
Samsung Electronics Co,. Ltd.
Tu Christine T.
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