Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-20
2003-09-23
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S173000, C438S176000, C438S191000, C438S192000, C438S195000, C438S199000, C438S206000, C438S268000, C438S269000, C438S212000, C438S279000, C257S328000, C257S365000, C257S302000
Reexamination Certificate
active
06624032
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on a semiconductor substrate. More particularly, the present invention relates to the fabrication of dual gate floating body MOS transistors.
2. Description of Related Art
As the semiconductor industry moves to smaller device feature sizes for ultra large scale integration (ULSI), transistor performance is expected in general to improve. However, the increased short channel effects due to the smaller feature sizes tends to limit the improved transistor performance. For example, in the past, field effect transistors (FETs) had gate electrodes and interconnecting lines made of polysilicon with widths that were greater than a micrometer (&mgr;m). Now the widths are much less than 0.15 &mgr;m, which leads to increased short channel effects. The increase in short channel effects results in higher transistor off state leakage, reduced current drive, and increased transistor variation, all of which are detrimental in current day ULSI applications.
Silicon-on-insulator (SOI) technology, an important integrated circuit technology, deals with forming transistors in a layer of semiconductor material that overlies an insulating layer. A common embodiment of SOI structures has a single crystal layer of silicon that overlies a layer of silicon dioxide. High performance and high density integrated circuits are achievable using SOI technology, because of the reduced parasitic elements that are present in the integrated circuits that use SOI transistors. Problems exist with SOI transistor technology, however, relating to the floating body in partially depleted SOI technology.
ULSI MOSFET devices are being continuously scaled down in channel length due to the increasing need for higher packing density and higher device speed. However, the continuous scaling down of geometry requires new transistor structures. Some innovative device structures and processes have been proposed that achieve the high performance of these small geometry devices, and yet can be made without requiring complicated fabrication techniques. One such device structure is a vertical MOSFET structure that provides a dual gate device which solves the floating body problem of partially depleted SOI transistors. A second important advantage of vertical MOS transistor technology is that the channel length scaling is not limited by the minimum lithographic resolution. The transistor channel length is instead determined by shallow trench etching and epitaxial layer growth techniques.
Transistors having two gate electrodes are known in the art, wherein there is a top gate and a bottom gate that may or may not be inherently self-aligned to the source/drain. N-channel double-gate MOSFET's with a 25 nm thick silicon channel have been successfully demonstrated. However, the process flow used to fabricate the two gate electrodes is complex and often uses non self-aligned source and drains. Further, although fully depleted floating body MOS devices have been proposed using planar transistors and SOI technology, they do not offer voltage control on the second gate, they require advanced SOI, advanced start material (thin body, thin box), and shallow trench isolation (STI). Thus, an improved structure and process flow allowing for fabrication of dual gate floating body NMOS and PMOS transistors is desired.
SUMMARY OF THE INVENTION
A dual gate transistor device and method for fabricating the same is described. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a first and a second gate electrode are formed next to the gate oxide layer, and a drain region is formed on the channel. After the drain is formed, an interlayer dielectric (ILD) layer is deposited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.
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Alavi Mohsen
Andideh Ebrahim
Bohr Mark T.
Thompson Scott
Keshavan B V
Smith Matthew
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