Clock induced supply noise reduction method for a latch...

Details Clock induced supply noise reduction method for a latch... Clock induced supply noise reduction method for a latch...

2001-07-31

2003-04-15

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S021000, C326S094000, C327S379000, C327S034000

Reexamination Certificate

active

06549030

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates generally to electronic circuitry. More specifically, the invention relates a method for reducing the noise associated with a clock signal for a latch based circuit.
2. Background Art
In all microprocessor-based systems, including, the clock circuit is a critical component. The clock circuit generates a clock signal that is a steady stream of timing pulses that synchronize and control the timing of every operation of the system.
FIG. 1
shows a prior art diagram of an ideal clock signal
10
. An entire clock cycle
12
includes a rising or leading edge
14
and a falling or trailing edge
16
. These edges
14
,
16
define the transition between the low phase and high phase of the signal.
FIG. 2
shows a block diagram of a prior art local clock signal distribution system. The clock signal
30
a
is input to a clock header
32
which serves to buffer the clock signal. From the header
32
, the clock signal
30
b
is input to an edge-triggered latch
34
where it serves to trigger the latch. A latch is a memory device that is commonly used in integrated circuits. It is dependent upon a clock signal to initiate its function. Latches take input data and distribute output data during the entire clock high phase. Most data tends to be waiting at the latch by the time the clock pulses high, therefore most latches switch on the rising edge of the clock. Latches are also made to work on the clock low phase and consequently tend to switch on the falling edge of the clock. Both types of latches are commonly used in order make use of both phases of the clock for computation.
FIG. 3
shows a digital logic schematic of the prior art local clock signal distribution system as shown in FIG.
2
. The clock signal
30
a
is input to the clock header
32
. The clock header
32
includes a NAND gate
36
and an inverter
38
a
. Once inside the clock header
32
, the clock signal
30
a
is one of the inputs to the NAND gate
36
. The other NAND input
42
is a signal that is HIGH so that the gate
36
simply inverts the value of the clock signal
30
a
. This NAND input
42
is switched to LOW to turn off the clock header
32
if needed. Next, the signal
30
a
passes through the inverter
38
a
which inverts the signal back to its original value. The clock signal
30
b
then passes from the clock header
32
to the latch
34
. Once in the latch
34
, the signal
30
b
is split into two paths. The first path passes through one inverter
38
b
, and the second path passes through two consecutive inverters
38
c
and
38
d
. Each path feeds into separate control transistors
40
a
and
40
b
that control the DATA_IN
44
and DATA_OUT
46
paths of the latch
34
.
Clock induced supply noise (hereafter “clock noise”) problems on the system power grid are usually caused by the large amount of current that is used in clock signal distribution. This current comes from the switching transistors that are controlled by the clock signal. As these transistors switch states, the current noise spikes onto the power grid due to the current demand or “current draw” of the switching transistors. These high current demands cause noise in the system voltage supply due to voltage (IR) drops and inherent system inductance (L di/dt). A clock signal distribution circuit uses a significant amount of current in a short amount of time because the spikes occur twice per clock cycle: once on the current draw of the leading edge and once on the current draw of the falling edge of the signal. This puts the noise at a very high frequency (2× the clock frequency). This noise can cause missed timing if the power supply is too low or component failure if the power supply voltage is too high. The noise can even escape “off the chip” and affect the other components of the system.
FIG. 4
shows a graph of current draw during a clock cycle period of a latch based circuit. The circuit could use both rising edge latches and falling edge latches. The value “I”
35
represents the full value of a current draw. The value “¾ I”
37
represents 75% of the full value while the value “½ I”
39
represents 50% of the full value. The first current draw
41
of the graph represents the draw that results from the leading edge of a clock cycle (at clock cycle =0). The second current draw
43
represents the draw that results from the falling edge of the clock cycle (at clock cycle =t/2). As shown, the leading edge draw
41
is the full value (“I” ) of current draw. The trailing edge draw
43
is the same value of the leading edge draw
41
. Also, each of the current draws
41
and
43
have a duration (“d”) 45 when the value is above “½ I”
39
.
A common technique to alleviate noise is adding additional power to the grid. This power is added upon sensing a voltage drop due to noise. However, such techniques only respond to noise at a much lower frequency than clock noise and also respond only to a certain threshold of noise. Consequently, a need exists for a technique that generates a response to clock noise at a synchronized frequency with the clock noise itself.
SUMMARY OF INVENTION
In some aspects, the invention relates to a method for reducing noise of a clock signal for a latch-based circuit, comprising: storing a charge upon receipt of a first signal; and dumping the charge onto a system power grid upon receipt of a second signal, wherein storing the charge and dumping the charge are synchronized with the operation of at least one latch.
In another aspect, the invention relates to a method for reducing noise of a clock signal for a latch-based circuit, comprising: step of storing a charge upon receipt of a first signal; step of dumping the charge onto a system power grid upon receipt of a second signal; and step of synchronizing storing the charge and dumping the charge with the operation of at least one latch.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 5539337 (1996-07-01), Taylor et al.
patent: 5672990 (1997-09-01), Chaw
patent: 5852378 (1998-12-01), Keeth
patent: 5926042 (1999-07-01), Talaga, Jr.
patent: 6072346 (2000-06-01), Ghahremani
patent: 6201431 (2001-03-01), Allen et al.

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