Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2001-03-22
2003-01-21
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S154000, C365S226000
Reexamination Certificate
active
06510088
ABSTRACT:
BACKGROUND OF THE INVENTION
A. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more specifically, it relates to a semiconductor integrated circuit device having reduced leakage and also to a method of operating a semiconductor integrated circuit device to reduced leakage.
B. Description of the Related Art
Transistors, or more specifically, metal oxide semiconductor field effect transistors (“MOSFETs”), are one of the most important devices in semiconductor integrated circuits. A transistor basically includes a gate and a channel with two ends. By controlling the voltage applied to the gate, the transistor can be used to control the flow of electricity through the channel and thereby turn on or turn off the flow of electric current between the two ends of the channel. For example, an N-type transistor can be turned off by applying no bias at its gate end and can be turned on by applying a voltage higher than the threshold voltage V
T
of the transistor. This functional characteristic enables a transistor to be operated and combined with other devices or transistors to form almost a variety of circuits. One example includes coupling a transistor or transistors with a storage cell to operate the reading, writing, or refreshing of a signal stored in the storage cell.
FIG. 1
illustrates the basic structure of a single dynamic random access memory (“DRAM”) storage cell. The cell includes a passing transistor
10
and a storage node of a capacitor
12
. The gate
10
g
of the transistor
10
is usually connected to a “word line” of a memory circuit that controls the reading, writing, or refreshing of the signal stored in the capacitor
12
. The signal in the capacitor
12
was inputted to or outputted from a “bit-line” (“BL”) of the memory circuit through the passing transistor
10
.
FIG. 2
illustrates the basic structure of a single static random access memory (“SRAM”) storage cell that includes two passing transistors
20
a
and
20
b
and a storage node consisting of two cross-coupled inverters
22
a
and
22
b
. The gates of the transistors
20
a
and
20
b
are usually connected the same word line that controls the reading, writing, or refreshing of the signal stored in the SRAM storage cell. The signal in the storage cell is usually communicated with the same bit line through the passing transistors
20
a
and
20
b.
One goal of the continuing development of semiconductor devices is to reduce the feature size of semiconductor devices and thereby reduce the operating power while at the same time increase the operating speed of the devices. A typical transistor operated through a controlling voltage applied to the gate of the transistor usually has a leakage problem that results in the flow of a current through the channel of the transistor even when the transistor is turned off. As the feature size of the transistor becomes smaller and the operating current of devices drops lower, the leakage of the transistor becomes comparatively larger. Typical leakage problems include drain-induced barrier lowing (“DIBL”), gate-induced drain leakage (“GIDL”), P/N junction leakage, subthreshold
In the applications of memory devices, leakage problems of their accompanying transistors often impair the performance of the memory devices. Taking SRAM as an example, the leakage of passing transistors increases the power consumption of a memory device and sometimes even affects the data validity of the signal stored in the storage cell. Taking DRAM as another example, the leakage of the passing transistor which keeps drawing current out of the storage cell of a capacitor affects the data validity of the signal stored in the storage cell.
A traditional approach towards solving the leakage problem is to apply a negative bias at the body end, or the substrate end, of an N-type transistor. Applying a negative substrate bias raises the threshold voltage of the N-type transistor and improves the data validity in a storage cell coupled with the transistor. The approach, however, does not work well for very deep submicron devices of a feature size smaller than 2 &mgr;m. For those devices, the concentration of the P-well of the N-type transistor is usually larger than 2×10
18
N/cm
3
and the increase of the junction leakage between the drain and the body (substrate) of a transistor makes the approach of applying the negative bias infeasible.
In the U.S. Pat. No. 5,781,481, Iwakiri proposed the idea of applying a negative bias on the gate of a passing transistor to reduce leakage solution. The actual implementation of this idea, however, requires the addition of a word-line level-shift circuitry within the limited space of word-line area on an integrated-circuit chip, making this approach difficult to implement in ordinary integrated-circuit chips under the general space limitations.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor integrated circuit device having reduced leakage that substantially obviates one or more of the problems due to the limitations and disadvantages of the related art.
The present invention also directed to the method of operating a semiconductor integrated circuit device with reduced leakage that substantially obviates one or more of the problems due to the limitations and disadvantages of the related art.
The invention also discloses a semiconductor integrated circuit device with a bias application device and a method of operation of a semiconductor integrated circuit device that applies a bias to the substrate of a transistor.
One of the advantages of the present invention includes a greater reduction in leakage than conventional operating schemes for transistors. Additional features and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the written description and claims hereof, as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention comprises an integrated circuit, including a passing transistor and a bias-application device. The present invention has the passing transistor coupled to a storage cell. The biased-application device is coupled to the substrate of the passing transistor and the storage cell. The bias-application device applies a first bias voltage of a positive value when the passing transistor is inactivated and applies a second bias voltage when the passing transistor is activated, wherein the second bias voltage is equal to or smaller than the first bias voltage. Further in accordance with the invention, there is provided a method of reducing the leakage of the passing transistor of N-type. The passing transistor is coupled with a storage cell. The method includes the applying a first bias voltage of a positive value when the passing transistor is inactivated, and applying a second bias voltage when the passing transistor is activated, wherein the second bias voltage is equal to or smaller than the first bias voltage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description, serve to explain the principles of the invention.
REFERENCES:
patent: 4904885 (1990-02-01), Yamada et al.
patent: 5471421 (1995-11-01), Rose et al.
patent: 5524095 (1996-06-01), Someya et al.
patent: 5708599 (1998-01-01), Sato et al.
patent: 5781481 (1998-07-01), Iwakiri
patent: 5880620 (1999-03-01), Gitlin et al.
patent: 5900665 (1999-05-01), Tibita
patent: 6061267
Chen Wei-Fan
Lien Chen-Hsin
Lin Shi-Tron
Auduong Gene N.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Nelms David
Winbond Electronics Corporation
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