Semiconductor chip that isolates DRAM cells from the...

Details Semiconductor chip that isolates DRAM cells from the... Semiconductor chip that isolates DRAM cells from the...

2001-05-03

2003-07-08

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S220000, C438S224000, C438S228000, C438S241000, C438S276000, C438S414000

Reexamination Certificate

active

06589834

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention.
The present invention relates to semiconductor chips having dynamic random access memory (DRAM) cells and, more particularly, to a semiconductor chip that isolates the DRAM cells from the peripheral and other functional circuitry, and reduces the leakage current in the cells.
2. Description of the Related Art.
A dynamic random access memory (DRAM) cell is a memory device that retains data stored in the cell for only a short period of time even when power is continuously applied to the cell. As a result, a DRAM cell must be periodically refreshed to maintain the data stored in the cell.
FIG. 1
shows a cross-sectional diagram that illustrates a conventional DRAM cell
100
. As shown in
FIG. 1
, DRAM cell
100
includes an access transistor
102
which is formed in a p-type material
110
, and a capacitor
104
which is connected to transistor
102
.
Access transistor
102
, in turn, includes spaced-apart source and drain regions
112
and
114
which are formed in material
110
, and a channel region
116
which is defined between regions
112
and
114
. In addition, transistor
102
also includes an access gate
120
which is insulatively formed over channel region
116
.
As further shown in
FIG. 1
, capacitor
104
includes a lower plate
124
which is connected to drain region
114
, a dielectric layer
126
which is formed over lower plate
124
, and an upper plate
128
which is formed over dielectric layer
126
.
In operation, a logic “one” is written to DRAM cell
100
by first placing a programming voltage, such as five volts, on source region
112
while a storage voltage, such as five volts, is applied to the top plate
126
of capacitor
104
. The storage voltage applied to capacitor
104
attracts electrons to the lower plate
124
of capacitor
104
where the electrons begin to accumulate.
After placing a programming voltage on source region
112
, access gate
120
is pulsed with the programming voltage. This pulse turns on access transistor
102
which causes the electrons on the lower plate
124
of capacitor
104
to flow to source region
112
.
The electrons flow from the lower plate
124
of capacitor
104
to source region
112
because the lower plate
124
of capacitor
104
has a potential which is less than five volts (some of the applied voltage is dropped across dielectric layer
126
), while source region
112
is at five volts.
When the trailing edge of the pulse again turns off access transistor
102
, a positive potential is stored on the lower plate
124
of capacitor
104
due to the decreased number of electrons which are present on the lower plate
124
of capacitor
104
.
This positive potential, however, lasts only a short time because electrons from leakage currents are readily attracted to the positive potential. As a result, the positive charge stored on the lower plate
124
of capacitor
104
must be “refreshed” by periodically removing the electrons from the lower plate
124
of capacitor
104
.
Although some applications exist for a single DRAM cell, large numbers of DRAM cells, organized in an array, are formed on a semiconductor chip. In addition to the DRAM cells, the chip also includes peripheral circuits which control various aspects of the array, and may also include other functional circuits, such as a graphics accelerator, which have been integrated to operate with the DRAM cells.
The peripheral circuits include, for example, refresh circuits which maintain the data stored in the cells, row and column decoders which identify the cells which have been addressed, and sense amps which detect the states of the data held in the addressed cells.
FIG. 2
shows a cross-sectional drawing that illustrates a prior art semiconductor chip
200
. As shown in
FIG. 2
, chip
200
includes a p-type substrate
210
, and a first n-well
212
which is formed in substrate
210
. In addition, chip
200
also includes a p-well
214
which is formed in n-well
212
, and a second n-well
216
which is formed in substrate
210
. Due to the presence of three wells in substrate
210
, this arrangement is commonly referred to as a triple-well structure.
As further shown in
FIG. 2
, a p+ diffusion region
220
and a plurality of n-channel transistors, as represented by n-channel transistor
222
, are formed in p-type substrate
210
. N-channel transistor
222
, in turn, includes spaced-apart source and drain regions
224
and
226
, a channel region
230
which is defined between source and drain regions
224
and
226
, and a gate
232
which is insulatively formed over channel region
230
.
In addition, an n+ diffusion region
234
and a plurality of p-channel transistors, as represented by p-channel transistor
236
, are formed in n-well
216
. P-channel transistor
236
, in turn, includes spaced-apart source and drain regions
240
and
242
, a channel region
244
which is defined between source and drain regions
240
and
242
, and a gate
246
which is insulatively formed over channel region
244
. N-channel and p-channel transistors
222
and
236
, in turn, are utilized to implement the peripheral and any other functional circuitry, such as a graphics accelerator.
Further, an n+ diffusion region
248
is formed in n-well
212
, while a p+ diffusion region
250
and a plurality of DRAM cells, as represented by DRAM cell
252
, are formed in p-well
214
. DRAM cell
252
includes spaced-apart source and drain regions
254
and
256
, and a channel region
260
which is defined between regions
254
and
256
. In addition, DRAM cell
252
also includes an access gate
262
which is insulatively formed over channel region
260
, and a capacitor
264
which is formed over drain region
256
.
DRAM cells
252
are formed in p-well
214
, which is formed in n-well
212
, for isolation. One of the most important requirements of an array of DRAM cells is that the array be electrically isolated from the large number of noise electrons that are generated by the peripheral and any other functional circuits. (Graphics accelerators, for example, generate many noise electrons). Without this isolation, these noise electrons will quickly reduce the positive charge stored on the lower plate of capacitor
264
, thereby leading to a substantially increased refresh rate.
In operation, isolation is obtained by reverse-biasing the p-well to first n-well junction, the first n-well to p-type substrate junction, and the second n-well to p-type substrate junction. The p-well to first n-well junction is reverse biased by applying ground or a negative voltage to p+ diffusion region
250
, and a positive voltage, such as Vcc, to n+ diffusion region
248
.
The junction between first n-well
212
and p-type substrate
210
, and the junction between second n-well
216
and p-type substrate
210
are reverse biased by applying the positive voltage to n+ diffusion regions
234
and
248
while applying ground to p+ diffusion region
220
.
Although noise from the peripheral and other functional circuits is effectively eliminated by utilizing wells
212
and
214
, the data retention time of DRAM cell
252
is still limited by a small junction leakage current that injects electrons into drain region
256
.
Reverse-biased pn junctions inherently possess a small leakage current that results from thermally and other randomly generated electron-hole pairs that are formed within a diffusion length of the junction. When a logic one is stored by DRAM cell
252
, drain region
256
has a positive charge, while p-well
214
is connected to ground or a negative voltage. As a result, the junction between drain region
256
and p-well
214
is reverse biased which, in turn, causes electrons to be injected into drain region
256
.
In addition, the ion implantation process used to fabricate wells
212
and
214
damages the silicon lattice structure. As a result of this damage, gettering sites are often formed in the lattice in the junction region between drain region
256
and p-well
214
. These g

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