Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-21
2003-09-02
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S382000, C438S384000
Reexamination Certificate
active
06613625
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a complementary MOS semiconductor device having a resistor circuit, for which low voltage operation, low consumption power, and high drive power are required, more particularly, a power management semiconductor device such as a voltage detector (hereinafter referred to as a VD), a voltage regulator (hereinafter referred to as a VR), or a switching regulator (hereinafter referred to as an SWR), or an analog semiconductor device such as an operational amplifier or a comparator.
2. Description of the Related Art
Conventionally, many kinds of complementary MOS semiconductor devices having a resistor circuit using a resistor made of polycrystalline silicon or the like are used.
FIG. 3
shows an example of a structure of a conventional semiconductor device having a resistor circuit. The semiconductor device is composed of an N-channel MOS
214
(hereinafter referred to as an NMOS) transistor in which the gate electrode formed to a P-type semiconductor substrate
201
is made of N
+
-type polycrystalline silicon
221
, a P-channel MOS
215
(hereinafter referred to as a PMOS) transistor in which the gate electrode formed to an N-well region is made of N
+
-type polycrystalline silicon
221
as in the case of the NMOS
214
, and a resistor used for a voltage dividing circuit for dividing a voltage, a CR circuit for setting a time constant, or the like, which is formed on a field insulating film
206
. A complementary MOS (hereinafter referred to as a CMOS) structure is obtained by the NMOS transistor and the PMOS transistor.
In the complementary MOS (CMOS) semiconductor device having the resistor circuit, the N
+
-type polycrystalline silicon is often used for the gate electrode in view of a polarity thereof because of ease of manufacturing and stability of operation. In this case, from a relationship of work function between the gate electrode and the semiconductor substrate (well region), the NMOS transistor becomes a surface channel type. On the other hand, in the case of the PMOS transistor, a threshold voltage becomes about −1 V from the relationship of work function between the gate electrode and the semiconductor substrate. Thus, when impurity implantation is conducted for reducing the threshold voltage, the PMOS transistor becomes a buried channel type in which a channel is formed in the inner portion of the substrate, which is slightly deeper than the surface thereof. The buried channel type has an advantage of high mobility because a carrier is transferred through the inner portion of the substrate. However, when the threshold voltage is reduced, a subthreshold characteristic is greatly deteriorated, thereby increasing a leak current. Thus, it is difficult for the PMOS transistor to reduce a voltage and shorten a channel as compared with the NMOS transistor.
Also, as a structure capable of reducing a voltage in both the NMOS transistor and the PMOS transistor, there is a homopolar gate structure in which the polarity of the gate electrode is set to be equal to that of the transistor. According to this structure, U-polycrystalline silicon is used for the gate electrode of the NMOS transistor and P
+
-polycrystalline silicon is used for the gate electrode of the PMOS transistor. Thus, each transistor becomes a surface channel type. As a result, a leak current can be suppressed and a voltage can be reduced. However, there are the following problems in costs and characteristics. That is, when the gate electrodes having different polarities are formed, the number of manufacturing steps is increased and increases in a manufacturing cost and a manufacturing period are caused. Further, with respect to an inverter circuit as a most fundamental circuit element, generally, in order to improve area efficiency, the layout for the gate electrodes of the NMOS transistor and the PMOS transistor is made such that a connection through metal is avoided and a piece of polycrystalline silicon which is two-dimensionally continued from the NMOS transistor to the PMOS transistor or a polycide structure composed of a laminate of a polycrystalline silicon film and a high melting point metallic silicide film is used. Here, when the gate electrode is made of polycrystalline silicon
221
,
222
as a single layer as shown in
FIG. 4
, it is impractical because of a high impedance of a PN junction in the polycrystalline silicon. Also, when the gate electrode has a polycide structure as shown in
FIG. 5
, an N-type impurity and a P-type impurity each are diffused to respective gate electrodes having an inverse conductivity type through high melting point metallic silicide films
212
at high speed during heat treatment of steps. As a result, a work function is changed and a threshold voltage is unstable.
SUMMARY OF THE INVENTION
In order to solve the above problems, the following means is used for the present invention.
(1) According to the present invention, there is provided a method of manufacturing a semiconductor device comprising:
forming an element isolation insulating film on a semiconductor substrate by thermal oxidation;
forming a gate insulating film on the semiconductor substrate by thermal oxidation;
depositing a first polycrystalline silicon film at a thickness of 500 angstroms to 2500 angstroms on the gate insulating film;
doping the first polycrystalline silicon film with an impurity such that a concentration of the impurity is 1×10
18
atoms/cm
3
or higher to make a conductivity type of the first polycrystalline silicon film a P-type;
depositing a high melting point metallic silicide film having a thickness of 500 angstroms to 2500 angstroms on the first polycrystalline silicon film having the P-type;
depositing an insulating film having a thickness of 500 angstroms to 3000 angstroms on the high melting point metallic silicide film;
etching the first polycrystalline silicon film having the P-type, the high melting point metallic silicide film, and the insulating film to form a gate electrode;
depositing a second polycrystalline silicon film having a thickness of 500 angstroms to 2500 angstroms on the element isolation insulating film;
doping one of an entire region and a first region of the second polycrystalline silicon film with a first conductivity type impurity at a concentration of 1×10
14
atoms/cm
3
to 9×10
18
atoms/cm
3
;
doping a second region of the second polycrystalline silicon film with a second conductivity type impurity at a concentration of 1×10
14
atoms/cm
3
to 9×10
18
atoms/cm
3
;
etching the second polycrystalline silicon film to form a resistor composed of the second polycrystalline silicon film;
doping one of a portion of and an entire region of the first region of the second polycrystalline silicon film with the first conductivity type impurity at a concentration of 1×10
19
atoms/cm
3
or higher;
doping one of a portion and an entire region of the second region of the second polycrystalline silicon film with the second conductivity type impurity at a concentration of 1×10
19
atoms/cm
3
or higher;
forming an intermediate insulating film over the semiconductor substrate;
forming a contact hole in the intermediate insulating film over the semiconductor substrate; and
providing a metallic wiring in the contact hole.
(2) In the method of manufacturing a semiconductor device of the present invention, an impurity introducing method for the first polycrystalline silicon film is for an ion implantation of boron.
(3) In the method of manufacturing a semiconductor device of the present invention, an impurity introducing method for the first polycrystalline silicon film is for an ion implantation of BF
2
.
(4) In the method of manufacturing a semiconductor device of the present invention, an impurity introducing method for the first polycrystalline silicon film is a doped-CVD method of depositing the first polycrystalline silicon film while the impurity is mixed thereinto.
(5) In the method
Hasegawa Hisashi
Osanai Jun
Adams & Wilks
Cao Phat X.
Doan Theresa T.
Seiko Instruments Inc.
LandOfFree
Method of manufacturing a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3070086