Non-volatile memory dielectric as charge pump dielectric

Details Non-volatile memory dielectric as charge pump dielectric Non-volatile memory dielectric as charge pump dielectric

2002-05-16

2003-04-15

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S298000, C257S299000, C438S257000, C438S266000

Reexamination Certificate

active

06548855

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of non-volatile memory devices. More particularly, the invention relates to using a dielectric layer of a non-volatile memory device as the dielectric for a charge pump capacitor.
BACKGROUND OF THE INVENTION
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Typically, a non-volatile memory device includes a floating-gate electrode upon which an electrical charge is stored. The floating-gate electrode overlies a channel region residing between source and drain regions in a semiconductor substrate. The floating-gate electrode together with the source and drain regions form an enhancement transistor. By storing electrical charge on the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively high value. Correspondingly, when charge is removed from the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively low value. The threshold level of the enhancement transistor determines the current flow through the transistor when the transistor is turned on by the application of appropriate voltages to the gate and drain. When the threshold voltage is high, no current will flow through the transistor, which is defined as a logic 0 state. Correspondingly, when the threshold voltage is low, current will flow through the transistor, which is defined as a logic 1 state.
In a flash EEPROM device, electrons are transferred to a floating-gate electrode through a dielectric layer overlying the channel region of the enhancement transistor. The electron transfer is initiated by either hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage potential is applied to the floating-gate by an overlying control-gate electrode. The control-gate electrode is capacitively coupled to the floating-gate electrode, such that a voltage applied on the control-gate electrode is coupled to the floating-gate electrode. The flash EEPROM device is programmed by applying a high positive voltage to the control-gate electrode, and a lower positive voltage to the drain region, which transfers electrons from the channel region to the floating-gate electrode. The flash EEPROM device is erased by grounding the control-gate electrode and applying a high positive voltage through either the source or drain region of the enhancement transistor. Under erase voltage conditions, electrons are removed from the floating-gate electrode and transferred into either the source or drain regions in the semiconductor substrate.
The high positive voltage required to program, read or erase such memory devices is typically greater than the input supply voltage. To develop the required high voltage levels for programming and erasing, a charge pump is employed within the memory device to multiply or “step up” the incoming supply voltage. A charge pump is a device readily incorporated onto a memory device which can be used to generate and maintain an internal supply voltage from an external supply voltage. The charge pump typically increases a small input voltage into a larger voltage that is used within the memory device. The charge pump usually includes a number of connected pump stages that are driven by two non-overlapping clock signals, and each pump stage consists of at least one charge pump capacitor. During the first clock cycle, each pump stage is connected effectively in a parallel configuration and will be charged up to the input supply voltage. During the next clock cycle, the banks are switched to a serial configuration, thus multiplying the amplitude of the input supply voltage. The actual voltage obtained at the charge pump output terminal depends upon the number of pump stages, the clock frequency, and on the charge transfer efficiency of each pump stage.
Present fabrication methods for memory devices employ separate processing steps for the creation of a memory device dielectric layer and a charge pump capacitor dielectric layer. Additionally, the charge pump capacitor presently occupies a significant portion of the total memory device area. A continuing goal in semiconductive wafer fabrication processes is to minimize processing steps, and particularly to minimize transfers of semiconductive wafers between separate processing chambers. Accordingly, it would be desirable to develop fabrication processes wherein fabrication steps could be eliminated. Furthermore, it also would be desirable to reduce the size of the charge pump capacitor.
SUMMARY OF THE INVENTION
In the light of the foregoing, it is an object of this invention to provide a method for reducing the number of processing steps for the creation of a non-volatile memory device, and to reduce the size of a charge pump capacitor within the non-volatile memory device.
A first embodiment of the present invention provides a non-volatile memory device having a memory cell array which includes a plurality of non-volatile memory cells. Each cell is formed on a semiconductor substrate and includes a control gate layer and a dielectric layer interposed between the semiconductor substrate and the control gate layer. The non-volatile memory device further includes a charge pump for providing a stepped up voltage for programming, reading or erasing the plurality of non-volatile memory cells. The charge pump has at least one capacitor for producing the stepped up voltage, and the capacitor includes a dielectric layer interposed between two capacitor plates. The two capacitor plates are formed respectively by the semiconductor substrate and the control gate layer. The capacitor dielectric layer and the non-volatile memory cell dielectric layer are formed during the same processing step.
A second embodiment of the present invention provides a non-volatile memory device having a memory cell array which includes a plurality of non-volatile memory cells. Each cell is formed on a semiconductor substrate and includes a floating gate polysilicon layer and a control gate layer. A tunnel oxide layer is interposed between the floating gate polysilicon layer and the semiconductor substrate, and a dielectric layer is interposed between the floating gate polysilicon layer and the control gate layer. The non-volatile memory device further includes a charge pump for providing a stepped up voltage for programming, reading or erasing the plurality of non-volatile memory cells. The charge pump has at least one capacitor for producing the stepped up voltage, and the capacitor includes a dielectric layer interposed between two capacitor plates. The two capacitor plates are formed respectively by the semiconductor substrate and the control gate layer. The capacitor dielectric layer and the non-volatile memory cell dielectric layer are formed during the same processing step.
A third embodiment of the present invention includes a method for creating a non-volatile memory device. The method includes forming a diffusion well in a semiconductor substrate and depositing a dielectric layer over the semiconductor substrate. A first gate charge trapping dielectric and a charge pump capacitor dielectric are formed by patterning the dielectric layer to remove a portion of the dielectric layer from a periphery area of the semiconductor substrate. A gate oxide is formed in the periphery area and a control gate is deposited over the fir

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