Method and/or architecture for implementing queue expansion...

Details Method and/or architecture for implementing queue expansion... Method and/or architecture for implementing queue expansion...

2000-11-16

2003-09-23

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S154000

Reexamination Certificate

active

06625711

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing multiqueue devices generally and, more particularly, to a method and/or architecture for implementing queue expansion of multiqueue devices. BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a conventional system
10
for implementing multiqueue first-in first-out (FIFO) devices is shown. The system
10
includes a selector section
12
, a selector section
14
and a number of memory sections
16
a
-
16
n
. The memory sections
16
a
-
16
n
are each implemented as FIFO devices. The conventional system implements each of the FIFOs
16
a
-
16
n
as an independent physical memory.
The selector section
12
receives data from a write interface and presents the data to one of the memory sections
16
a
-
16
n
in response to a write select signal WR_SEL. The selector section
12
selects one of the FIFOs
16
a
-
16
n
based on the signal WR_SEL. The incoming data is then stored into the appropriate FIFO
16
a
-
16
n
. Similarly, the selector section
14
presents data to a read interface from one of the memory sections
16
a
-
16
n
in response to a read select signal RD_SEL. The selector section
14
selects one of the FIFOs
16
a
-
16
n
based on the signal RD-SEL and reads the data from the appropriate FIFO
16
a
-
16
n.
Referring to
FIG. 2
, a diagram of the control signals of the system
10
implementing a single master device implementation is shown. The multiqueue FIFO
10
is implemented without queue expansion capabilities. The FIFO
10
has a number of write signals (that are shown beginning with W), a number of read signals (that are shown starting with a R), and a number of other signals. The current definition of control and status signals of a single master cannot support queue expansion.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a plurality of devices configured to store and present data to a plurality of queues. Each of the plurality of devices may be configured to receive (i) one or more first control signals configured to control data transfer and (ii) one or more second control signals to configure the plurality of queues. A particular one or more of the plurality of devices may be selected in response to one or more device identification bits.
The objects, features and advantages of the present invention include providing a method and/or architecture for queue expansion of multiqueue devices that may provide (i) device identification (ID) inputs for determining queue/register address most significant bits (MSB) that may include (a) write queue address expansion most significant bits for writing into the expanded queues, (b) write management register address expansion most significant bits for accessing registers belonging to other appropriate devices, (c) read queue address expansion most significant bits for reading from the expanded queues, and/or (d) read management register address expansion most significant bits for accessing registers belonging to the other appropriate devices, (ii) tristatable output data buses and control buses for arbitration, (iii) an interface for synchronous status polling across devices, (iv) a faster clock synchronization interface, and/or (v) variable size packet handling capacity.


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