Method and circuitry for controlling clocks of embedded...

Details Method and circuitry for controlling clocks of embedded... Method and circuitry for controlling clocks of embedded...

2002-04-19

2003-09-02

Le, Don (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S038000, C326S016000

Reexamination Certificate

active

06614263

ABSTRACT:

The present invention relates, in general, to the design and testing of integrated circuits and, more specifically, to a method of designing circuits having a hierarchical structure so as to provide improved test clock distribution circuitry and to integrated circuits produced by the method.
BACKGROUND OF THE INVENTION
As integrated circuits continue to become more complex and circuits are designed in a hierarchical fashion, it is becoming increasingly more difficult to distribute clock signals for both normal operational mode and in test mode in way that allows easy design and verification of tests for individual cores compatible with conventional design methods. One difficulty resides with the distribution of clock signals to selected cores during both testing of one or more selected cores and normal operation of the circuit. In some instances, it may be desired to test a core in isolation or independently of other cores. In other instances, it may be desired to test one or more selected cores while other cores are disabled or operated in functional mode. Still another difficulty is to provide a clock distribution method that is compatible with existing clock tree synthesis and layout methods, particularly in situations where clock trees span multiple cores. The clock distribution method must also provide a mechanism to control power consumption during test while also being flexible to accommodate different power consumption limits at different manufacturing stages. It is also important to preserve the level of synchronicity of the functional clock domains at all levels of test. In other words, the clock distribution method must keep clocks that span multiple cores synchronous to each other in top level tests in the same manner that this occurs in functional mode.
It will be seen that there is a for a test clock distribution method that allows at-speed testing of chip logic designed in an hierarchical fashion.
SUMMARY OF THE INVENTION
The present invention seeks to provide method of designing integrated circuits having embedded blocks or cores in a manner which will facilitate the distribution of clock signals to various clock domains and cores during both normal operation and testing of the cores and circuit.
One aspect of the invention is generally defined as a method of designing an integrated circuit for distributing test clock signals to embedded cores having at least one core functional clock input, the method comprising, for each core, providing a clock gating circuit for selectively disabling a core functional clock signal applied to a core primary clock input; and providing a core clock selection circuit for each secondary core functional clock input for selecting one of a core functional clock signal output by the gating circuit and a core test clock signal and applying a selected signal to the each secondary core functional clock input.
Another aspect of the invention relates to a novel circuit produced by the method of the present invention. This aspect of the invention is generally defined as a test clock distribution circuit for an integrated circuit having a plurality of embedded cores each having one or more functional clock inputs, comprising each core having a clock gating circuit for selectively disabling a core functional clock signal applied to a core primary clock input; and a clock selection circuit for each secondary core functional clock input for selecting between a core functional clock signal output by the gating circuit and a core test clock signal.
A still further aspect of the invention relates to a method of testing an integrated circuit having embedded cores and designed according to the method of the present invention. This aspect of the invention is generally comprises enabling core functional clock signals of selected cores by applying an inactive core clock disable signal to a clock gating circuit of the selected cores; selecting a test clock signal by applying an active core test enable signal to a clock selection circuit of the selected cores; disabling the core functional clock signals of non-selected embedded cores by applying an active core clock disable signal to respective clock gating circuits thereof in a manner that will preserve the state of memory elements in the other embedded cores and/or reduce the amount of power required to operate the integrated circuit while the selected core is being tested; applying a clock signal to the circuit functional clock inputs connected to the clock gating circuit of selected embedded cores; and activating embedded test controllers in the selected cores so as to test the selected cores.


REFERENCES:
patent: 4800564 (1989-01-01), DeFazio et al.
patent: 5336950 (1994-08-01), Popli et al.
patent: 5651013 (1997-07-01), Iadanza
patent: 5850150 (1998-12-01), Mitra et al.

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