Semiconductor memory device enabling reliable stress test...

Details Semiconductor memory device enabling reliable stress test... Semiconductor memory device enabling reliable stress test...

2002-07-17

2003-03-25

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S230060

Reexamination Certificate

active

06538935

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a spare memory cell.
2. Description of the Background Art
In general, a semiconductor memory device has a spare memory cell for replacing a defective memory cell. When a defect is found in a normal memory cell, it is replaced with a spare memory cell on the basis of a word line or a column select line.
Initially, a semiconductor memory device is tested in a wafer state. When a defective memory cell is found by this test, an address of the defective memory cell is stored in a spare determination circuit of an address decoder. This storing operation is sometimes called programming.
For example, the spare determination circuit includes a fuse element, and the address of the defective memory cell is programmed by selectively blowing the fuse element by a laser beam or the like.
In a repaired chip after replacement of the defective memory cell, the spare memory cell rather than the normal memory cell is selected when the address corresponding to the defective memory cell is input. Therefore, when the replacement takes place, only the spare memory cell will be accessible for the certain address.
FIG. 12
shows an arrangement of memory cells related to a select operation of a conventional memory cell.
Referring to
FIG. 12
, a defective memory cell is replaced on the basis of a word line or a column select line.
As an example, a bit defect existing in a memory cell corresponding to an intersection of a word line WL
1
and a bit line BL
4
is described. A bit defect means a defect occurring in one memory cell. Other defects include a word line defect which is a disconnection of a word line, a bit line defect which is a disconnection of a bit line, and the like. A chip with the word line defect can only be repaired by replacing the memory cell on the basis of a word line. Similarly, a chip with the bit line defect can only be repaired by replacing the memory cell on the basis of a column select line.
Meanwhile, the bit defect can be repaired by a row replacement, i.e., selecting a spare word line SWL
0
in place of a word line WL
1
, or by a column replacement, i.e., selecting a spare column select line SCSL
0
in place of a column select line CSL
4
.
FIG. 12
shows an example of a replacement of a memory cell by selecting the spare column select line SCSL
0
in place of the column select line CSL
4
in a chip having the bit defect.
With such replacement, the semiconductor memory device can operate normally even if a bit defect exists.
However, to ensure reliability of a semiconductor memory device, sometimes a stress is applied after the replacement of the memory cell for a reliability check operation test. Such test includes, for example, a burn-in test which removes an early defect by an acceleration test.
In
FIG. 12
, a pattern is written to a memory cell array so that the data held by adjacent memory cells will be opposite to each other. A minor leak defect between an object memory cell and the adjacent memory cell can be removed by writing such a pattern.
However, as the replacement is performed by selecting the spare column select line SCSL
0
in place of the column select line CSL
4
, desired data will not be written to the memory cells (the memory cell column including the bit defect) which should be selected by the column select line CSL
4
if it were not for the bit defect. Thus, a sufficient stress cannot be applied to a memory cell group selected by column select lines CSL
3
and CSL
5
which are adjacent to the memory cell column including the bit defect.
FIG. 13
shows a problem caused by a replacement of a memory cell on the basis of a word line.
Referring to
FIG. 13
, when a replacement is performed by selecting a spare word line SWL
0
in place of a word line WL
8
, a problem similar to that described with reference to
FIG. 12
occurs. That is, the test performed by applying a stress to a memory cell with a write data pattern is not fitted for the semiconductor memory device in which the replacement is performed.
In
FIG. 13
, a pattern is written to a memory cell array so that the data written to adjacent memory cells will be opposite to each other.
However, the word line WL
8
will not be activated since the replacement is performed by selecting the spare word line SWL
0
in place of the word line WL
8
. Thus, desired data will not be written to the memory cells (the memory cell row including the bit defect) which should be selected by the word line WL
8
if it were not for the bit defect. Therefore, a sufficient stress cannot be applied to a memory cell group selected by word lines WL
7
and WL
9
which are adjacent to the memory cell row including the bit defect.
As shown in
FIGS. 12 and 13
, when the memory cell is replaced with the spare memory cell and when the test is performed by applying a stress to a memory cell with a write data pattern, the stress applied to the periphery of the replaced region will be insufficient.
In particular, after the defect such as one bit defect was repaired, most of the memory cells connected to the word line or the column select line used for selecting the defective memory cell are normally accessible. Therefore, the reliability will be enhanced by writing data and applying a stress to this region.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device ensuring high reliability even when a spare memory cell is used.
The present invention is summarized as a semiconductor memory device having a test mode and a normal mode as operation modes, including a plurality of normal memory cells, a plurality of spare memory cells and an address decode circuit.
The plurality of spare memory cells are used to replace a part of the plurality of normal memory cells in the normal mode.
The address decode circuit decodes an address signal and specifies a part of the sum of the plurality of normal memory cells and the plurality of spare memory cells.
If a write address provided by the address signal matches with a replacement address on data writing in the normal mode, the address decode circuit selects, in place of a first portion of the plurality of normal memory cells which corresponds to the address signal, a second portion of the plurality of spare memory cells which corresponds to the first portion.
On the other hand, if the write address matches with the replacement address on data writing in the test mode, the address decode circuit selects both of the first portion and the second portion.
Therefore, the principal advantage of the present invention is the ability to provide a semiconductor memory device having enhanced reliability even when a normal memory cell is replaced with a spare memory cell. That is, if data can be written to the most part of the replaced portion such as in the case of one bit defect, data can also be written to the replaced normal memory cells in the test mode, so that the regular stress can be applied to the peripheral portion of the replaced normal memory cells in the stress test.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 4860260 (1989-08-01), Saito et al.
patent: 6297997 (2001-10-01), Ohtani et al.
patent: 6469943 (2002-10-01), Ochi

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