Signal transmission system

Details Signal transmission system Signal transmission system

2001-08-01

2003-07-29

Le, Don (Department: 2824)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S027000, C326S082000

Reexamination Certificate

active

06600336

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a signal transmission system effectively applicable to a system LSI, for example.
Recently, to enhance the performance of a system LSI, the index of parallelism, not the clock frequency, of the LSI is increased more and more often. For example, in handling multimedia-related data (i.e., audiovisual data including pictures or music), multiple circuits may be laid out in parallel with each other and coupled to a bus with an increased width, thereby processing the data in parallel and increasing the substantial computation rate. The bus width may also be increased to compensate for the low operating speed of a memory (e.g., a built-in DRAM) for storing the data thereon and thereby increase the effective data transfer rate. For that purpose, a data bus with as broad a width as 4096 bits is sometimes used. However, when data is transferred from a certain block to another by way of a bus of such a broad width, a huge quantity of power is dissipated on the signal lines included in the bus (which will be herein referred to as “bus lines”).
Hereinafter, it will be estimated with reference to
FIGS. 16 through 18
how much power is dissipated on an 8-bit bus.
FIG. 16
schematically illustrates stray capacitances Ch and Cv, associated with bus lines for a known signal transmission system, as a cross section of a semiconductor substrate. In the illustrated example, an 8-bit bus is made up of eight bus lines B[
7
] through B[
0
] that are equally spaced apart from each other horizontally. As shown in
FIG. 16
, two ground lines GND are laid out on the right- and left-hand sides of the bus lines B[
0
] and B[
7
], respectively, and are also equally spaced apart horizontally therefrom. The space S between two adjacent ones of the bus lines B[
7
] through B[
0
] is supposed to be equal to the space S between the ground line GND and the bus line B[
7
] or B[
0
]. Furthermore, in the example illustrated in
FIG. 16
, these bus lines B[
7
] through B[
0
] and ground lines GND have a thickness T
1
and are vertically spaced apart from their underlying structure (which may be either substrate or lower-level interconnect but which is shown as GND in the example illustrated in
FIG. 16
) by a distance T
2
. The distance T
2
is actually equal to the thickness of an interlevel film existing between the bus lines B[
7
] through B[
0
] or ground lines GND and the underlying structure. The bus lines B[
7
] through B[
0
] and ground lines GND with a width L are arranged at regular pitches P and are horizontally spaced apart from each other by the space S. For example, T
1
=T
2
=1,000 nm, P=1.0 &mgr;m, L=0.26 &mgr;m and S=0.74 &mgr;m. According to the 0.18 &mgr;m design rule, the line space S can be decreased down to about 0.2 &mgr;m. In the illustrated example, however, the line space S is intentionally increased more than threefold to 0.74 &mgr;m to minimize the stray capacitance Ch between two adjacent bus lines. In
FIG. 16
, Ch denotes a horizontal stray capacitance created between a given bus line and a horizontally adjacent bus or ground line, while Cv denotes a vertical stray capacitance created between a given bus line and the underlying structure.
If the capacitance associated with a line of a length of 4 mm is calculated by a boundary element method, the capacitance associated with the line per unit length (e.g., 1 mm) will be: Ch=0.090 pF/mm and Cv=0.025 pF/mm. Accordingly, even if the line space S is more than three times as long as the minimum value thereof, the horizontal components (i.e., 2×Ch, because two horizontal stray capacitances Ch exist on right- and left-hand sides of each bus line) account for almost all (i.e., 88% in this example) of the total capacitance (i.e., 2×Ch+Cv including the vertical component).
Next, it will be described with reference to
FIGS. 17 and 18
how charges are stored on each stray capacitance where 8-bit data words “AA” and “55” (which are both hexadecimal representations) are alternately transferred through the bus lines B[
7
] through B[
0
]. In each of these patterns (or data words), every adjacent pair of bits has mutually opposite values (i.e., “01” or “10”). Also, the respective bits making up the pattern “AA” are inverse of the counterparts making up the other pattern “55”. Specifically,
FIG. 17
illustrates how charges are stored during the transmission of the data pattern “AA”, while
FIG. 18
illustrates how charges are stored during the transmission of the data pattern “55”.
In the example illustrated in
FIG. 17
for the data pattern “AA”, two adjacent charges stored on each horizontal capacitance Ch have mutually opposite polarities. However, no charges have been stored on the capacitance Ch between the bus line B[
0
], representing the least significant bit (LSB), and the ground GND on the right-hand side of the bus line B[
0
] because these lines are at the same potential level. In
FIG. 17
, voltages are applied so that the two lines, adjacent to the rightmost and leftmost ones of the eight bus lines B[
7
] through B[
0
], and the underlying structure are grounded, and the charges stored have all been supplied from bus drivers. Over the respective bus lines B[
7
] through B[
0
], shown are the quantities Q
1
and Q
2
of charges that were supplied from a power supply when the previous data pattern “55” was replaced with this data pattern “AA”. Q
1
represents the quantity of charges stored in a capacitance between two adjacent bus lines and Q
2
represents the quantity of charges stored elsewhere as will be described in detail later. As for the vertical capacitances Cv on the other hand, charges have been stored, first, on the capacitance Cv associated with the bus line B[
7
] representing the most significant bit (MSB), and then on every other bit basis. That is to say, in the example illustrated in
FIG. 17
, the charges have been stored on only the “1” bits of the data pattern “AA”.
Suppose the data to be transferred has changed from the pattern “AA” shown in
FIG. 17
into the pattern “55” shown in FIG.
18
. In that case, each of the charges stored on every horizontal capacitance Ch between two adjacent bus lines has the same absolute value but the opposite polarity compared to the situation shown in FIG.
17
. However, the horizontal capacitance Ch between the leftmost bus line B[
7
] and the ground GND and the vertical capacitance Cv between the bus line B[
7
] and the ground GND have been discharged to lose the charges. On the other hand, the horizontal capacitance Ch between the rightmost bus line B[
0
] and the ground GND and the vertical capacitance Cv between the bus line B[
0
] and the ground GND have been charged with a current supplied from the bus driver to gain the charges. It should be noted that any capacitance is dischargeable with no current supplied from the power supply.
The charges are stored in this manner for the respective data patterns. Next, it will be described how much charging current flows from the power supply. It should be noted that the supply voltage is supposed to be 1 V for the sake of simplicity.
First, the quantity Q
1
of charges stored on each capacitance Ch between two adjacent bus lines where the patterns “AA” and “55” are transmitted alternately will be considered. For example, on the horizontal capacitance Ch between the two adjacent bus lines B[
7
] and B[
6
], a charge quantity Ch×1 V (with positive charges located on the right-hand side) is stored during the transmission of the pattern “55” as shown in
FIG. 18
, while a charge quantity Ch×1 V (with positive charges located on the left-hand side) is stored during the transmission of the pattern “AA” as shown in FIG.
17

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